<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29227">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Remove dev_find_slot where possible<br><br>The procedure dev_find_slot has 3 main uses. To find configuration<br>(devicetree), to verify if a particular device is enabled at build \<br>time, and to get the address for PCI access while in bootblock/romstage.<br>The third use can be hidden by using macros defined in pci_devs.h,<br>making it very clear what PCI device is being accessed. replace the<br>temporary pointers to device used with PCI access with SOC_XXX_DEV where<br>XXX is the device being accessed, and remove the setting of the temporary<br>pointers.<br><br>BUG=b:117917136<br>TEST=Build grunt.<br><br>Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/cpu.c<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/lpc.c<br>M src/soc/amd/stoneyridge/northbridge.c<br>M src/soc/amd/stoneyridge/southbridge.c<br>5 files changed, 25 insertions(+), 31 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29227/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c</span><br><span>index 92b2950..3741703 100644</span><br><span>--- a/src/soc/amd/stoneyridge/cpu.c</span><br><span>+++ b/src/soc/amd/stoneyridge/cpu.c</span><br><span>@@ -55,8 +55,8 @@</span><br><span> </span><br><span> static int get_cpu_count(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *nb = dev_find_slot(0, HT_DEVFN);</span><br><span style="color: hsl(0, 100%, 40%);">- return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ return (pci_read_config16(SOC_NB_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK)</span><br><span style="color: hsl(120, 100%, 40%);">+ + 1;</span><br><span> }</span><br><span> </span><br><span> static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index 27e1f70..78bed2a 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -98,6 +98,7 @@</span><br><span> /* D18F5 */</span><br><span> #define nb_capabilities2 0x84</span><br><span> #define cmp_cap_mask 0xff</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> enum {</span><br><span> /* SMM handler area. */</span><br><span> SMM_SUBREGION_HANDLER,</span><br><span>diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c</span><br><span>index 6833db6..317574b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/lpc.c</span><br><span>+++ b/src/soc/amd/stoneyridge/lpc.c</span><br><span>@@ -38,32 +38,30 @@</span><br><span> {</span><br><span> u8 byte;</span><br><span> u32 dword;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *sm_dev;</span><br><span> </span><br><span> /*</span><br><span> * Enable the LPC Controller</span><br><span> * SMBus register 0x64 is not defined in public datasheet.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- sm_dev = dev_find_slot(0, SMBUS_DEVFN);</span><br><span style="color: hsl(0, 100%, 40%);">- dword = pci_read_config32(sm_dev, 0x64);</span><br><span style="color: hsl(120, 100%, 40%);">+ dword = pci_read_config32(SOC_SMBUS_DEV, 0x64);</span><br><span> dword |= 1 << 20;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(sm_dev, 0x64, dword);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_SMBUS_DEV, 0x64, dword);</span><br><span> </span><br><span> /* Initialize isa dma */</span><br><span> isa_dma_init();</span><br><span> </span><br><span> /* Enable DMA transaction on the LPC bus */</span><br><span style="color: hsl(0, 100%, 40%);">- byte = pci_read_config8(dev, LPC_PCI_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL);</span><br><span> byte |= LEGACY_DMA_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, LPC_PCI_CONTROL, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte);</span><br><span> </span><br><span> /* Disable the timeout mechanism on LPC */</span><br><span style="color: hsl(0, 100%, 40%);">- byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);</span><br><span> byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte);</span><br><span> </span><br><span> /* Disable LPC MSI Capability */</span><br><span style="color: hsl(0, 100%, 40%);">- byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS);</span><br><span> /* BIT 1 is not defined in public datasheet. */</span><br><span> byte &= ~(1 << 1);</span><br><span> </span><br><span>@@ -73,15 +71,15 @@</span><br><span> * interrupt and visit LPC.</span><br><span> */</span><br><span> byte &= ~LPC_NOHOG;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte);</span><br><span> </span><br><span> /*</span><br><span> * Enable hand-instance of the pulse generator and SPI</span><br><span> * controller prefetch of flash.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- byte = pci_read_config8(dev, LPC_HOST_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL);</span><br><span> byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, LPC_HOST_CONTROL, byte);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte);</span><br><span> </span><br><span> cmos_check_update_date();</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>index 4e844af..d17d855 100644</span><br><span>--- a/src/soc/amd/stoneyridge/northbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/northbridge.c</span><br><span>@@ -47,27 +47,25 @@</span><br><span> u32 io_min, u32 io_max)</span><br><span> {</span><br><span> u32 tempreg;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span> </span><br><span> /* io range allocation. Limit */</span><br><span> tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)</span><br><span> | ((io_max & 0xf0) << (12 - 4));</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(addr_map, reg + 4, tempreg);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg);</span><br><span> tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(addr_map, reg, tempreg);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_ADDR_DEV, reg, tempreg);</span><br><span> }</span><br><span> </span><br><span> static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,</span><br><span> u32 mmio_min, u32 mmio_max)</span><br><span> {</span><br><span> u32 tempreg;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);</span><br><span> </span><br><span> /* io range allocation. Limit */</span><br><span> tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(addr_map, reg + 4, tempreg);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg);</span><br><span> tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(addr_map, reg, tempreg);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_ADDR_DEV, reg, tempreg);</span><br><span> }</span><br><span> </span><br><span> static void read_resources(struct device *dev)</span><br><span>@@ -153,8 +151,7 @@</span><br><span> </span><br><span> printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));</span><br><span> /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev_find_slot(0, ADDR_DEVFN),</span><br><span style="color: hsl(0, 100%, 40%);">- D18F1_VGAEN, VGA_ADDR_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);</span><br><span> }</span><br><span> </span><br><span> static void set_resources(struct device *dev)</span><br><span>@@ -379,17 +376,16 @@</span><br><span> </span><br><span> void fam15_finalize(void *chip_info)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev;</span><br><span> u32 value;</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, NB_IOAPIC_INDEX, 0);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, NB_IOAPIC_DATA, 5); /* TODO: move to dsdt.asl */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO: move IOAPIC code to dsdt.asl */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5);</span><br><span> </span><br><span> /* disable No Snoop */</span><br><span style="color: hsl(0, 100%, 40%);">- dev = dev_find_slot(0, HDA0_DEVFN);</span><br><span style="color: hsl(0, 100%, 40%);">- value = pci_read_config32(dev, HDA_DEV_CTRL_STATUS);</span><br><span style="color: hsl(120, 100%, 40%);">+ value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS);</span><br><span> value &= ~HDA_NO_SNOOP_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value);</span><br><span> }</span><br><span> </span><br><span> static void reserve_domain_res(unsigned int start, unsigned int end)</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index b188b76..6a94b4c 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -892,7 +892,7 @@</span><br><span> uintptr_t xhci_fw;</span><br><span> uintptr_t fwaddr;</span><br><span> size_t fwsize;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct device *sd, *sata, *ehci;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *sd, *sata;</span><br><span> </span><br><span> struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);</span><br><span> if (gnvs == NULL)</span><br><span>@@ -925,7 +925,6 @@</span><br><span> gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE;</span><br><span> gnvs->fw03 = fwsize << 16;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- ehci = dev_find_slot(0, EHCI1_DEVFN);</span><br><span> gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0)</span><br><span> & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29227">change 29227</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29227"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11 </div>
<div style="display:none"> Gerrit-Change-Number: 29227 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>