[coreboot-gerrit] Change in coreboot[master]: soc/intel: Consolidate FSP CAR setup and teardown code
PraveenX Hodagatta Pranesh (Code Review)
gerrit at coreboot.org
Mon Oct 22 14:21:50 CEST 2018
PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/29209
Change subject: soc/intel: Consolidate FSP CAR setup and teardown code
......................................................................
soc/intel: Consolidate FSP CAR setup and teardown code
This patch adds following changes,
- APL, CFL, DENVERTON soc's using same implementation to setup and
teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
and moved to common CPU car.
- Tempraminit parameters are passed from soc bootblock.c.
- Coffee lake Soc uses FSPT to support Intel Security features like
BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
by programming tempraminit parameters and add FSP_T_XIP default if
FSP_CAR is selected.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
without errors.
Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh at intel.com>
---
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/bootblock/bootblock.c
D src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/common/block/cpu/Makefile.inc
R src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
R src/soc/intel/common/block/cpu/car/exit_car_fsp.S
M src/soc/intel/denverton_ns/Makefile.inc
D src/soc/intel/denverton_ns/exit_car_fsp.S
10 files changed, 61 insertions(+), 196 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29209/1
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 632cb99..d2a9a1f 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -18,7 +18,6 @@
bootblock-y += pmutil.c
bootblock-y += spi.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
-bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
romstage-y += car.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
@@ -74,8 +73,6 @@
postcar-y += i2c.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
-postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
-
verstage-y += car.c
verstage-y += i2c.c
verstage-y += gspi.c
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index bc5c170..0ec80a0 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2018 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -34,6 +34,25 @@
#include <soc/pm.h>
#include <spi-generic.h>
#include <timestamp.h>
+#include <FsptUpd.h>
+
+const FSPT_UPD temp_ram_init_params = {
+ .FspUpdHeader = {
+ .Signature = 0x545F4450554C5041ULL, /* 'APLUPD_T' */
+ .Revision = 1,
+ .Reserved = {0},
+ },
+ .FsptCommonUpd = {
+ .Revision = 0,
+ .Reserved = {0},
+ .MicrocodeRegionBase = 0,
+ .MicrocodeRegionLength = 0,
+ .CodeRegionBase =
+ (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),
+ .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,
+ .Reserved1 = {0},
+ },
+};
static const struct pad_config tpm_spi_configs[] = {
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
deleted file mode 100644
index 4c4fa71..0000000
--- a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_def.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/cr.h>
-#include <cpu/x86/post_code.h>
-
-#include <../../../arch/x86/walkcbfs.S>
-
-#define FSP_HDR_OFFSET 0x94
-
-.global bootblock_pre_c_entry
-bootblock_pre_c_entry:
-
-.global cache_as_ram
-cache_as_ram:
- post_code(0x21)
-
- /* find fsp in cbfs */
- lea fsp_name, %esi
- mov $1f, %esp
- jmp walkcbfs_asm
-1:
- cmp $0, %eax
- jz .halt_forever
- mov CBFS_FILE_OFFSET(%eax), %ebx
- bswap %ebx
- add %eax, %ebx
- add FSP_HDR_OFFSET, %ebx
-
- /*
- * ebx = FSP INFO HEADER
- * Calculate entry into FSP
- */
- mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */
- add 0x1c(%ebx), %eax /* add the FSP ImageBase */
-
- /*
- * Pass early init variables on a fake stack (no memory yet)
- * as well as the return location
- */
- lea CAR_init_stack, %esp
-
- /* call FSP binary to setup temporary stack */
- jmp *%eax
-
-/*
- * If the TempRamInit API is successful, then when returning, the ECX and
- * EDX registers will point to the temporary but writeable memory range
- * available to the bootloader where ECX is the start and EDX is the end of
- * the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more
- * information.
- *
- * Return Values:
- * EAX | Return Status
- * ECX | Temporary Memory Start
- * EDX | Temporary Memory End
- * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call
- */
-
-CAR_init_done:
-
- /* Setup bootblock stack */
- mov %edx, %esp
-
- /* clear CAR_GLOBAL area as it is not shared */
- cld
- xor %eax, %eax
- movl $(_car_global_end), %ecx
- movl $(_car_global_start), %edi
- sub %edi, %ecx
- rep stosl
-
- /* We can call into C functions now */
- call bootblock_c_entry
-
- /* Never reached */
-
-.halt_forever:
- post_code(POST_DEAD_CODE)
- hlt
- jmp .halt_forever
-
-CAR_init_params:
- .long 0 /* Microcode Location */
- .long 0 /* Microcode Length */
- .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
- .long CONFIG_ROM_SIZE /* Total Firmware Length */
-
-CAR_init_stack:
- .long CAR_init_done
- .long CAR_init_params
-
-fsp_name:
- .ascii "blobs/fspt.bin\x00"
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index abe029a..161db33 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -75,6 +75,7 @@
select UDELAY_TSC
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
+ select FSP_T_XIP if FSP_CAR
config UART_DEBUG
bool "Enable UART debug port."
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 0aac186..805ae0e 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corporation..
+ * Copyright (C) 2017-2018 Intel Corporation..
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,6 +19,24 @@
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/pch.h>
+#include <FsptUpd.h>
+
+const FSPT_UPD temp_ram_init_params = {
+ .FspUpdHeader = {
+ .Signature = 0x545F4450554C4643ULL, /* 'CFLUPD_T' */
+ .Revision = 1,
+ .Reserved = {0},
+ },
+ .FsptCoreUpd = {
+ .MicrocodeRegionBase =
+ (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
+ .MicrocodeRegionSize =
+ (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
+ .CodeRegionBase =
+ (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),
+ .CodeRegionSize = (UINT32)CONFIG_ROM_SIZE,
+ },
+};
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc
index aa61ffc..5207227 100644
--- a/src/soc/intel/common/block/cpu/Makefile.inc
+++ b/src/soc/intel/common/block/cpu/Makefile.inc
@@ -1,10 +1,12 @@
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S
+bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
+postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c
diff --git a/src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
similarity index 82%
rename from src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S
rename to src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index b998c21..5bab9cd 100644
--- a/src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 - 2017 Intel Corp.
+ * Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,10 +19,8 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/cr.h>
#include <cpu/x86/post_code.h>
+#include <../../../../../arch/x86/walkcbfs.S>
-#include <../../../arch/x86/walkcbfs.S>
-
-#define FSP_HDR_OFFSET 0x94
.extern temp_ram_init_params
@@ -31,7 +29,7 @@
.global cache_as_ram
cache_as_ram:
- post_code(0x2f)
+ post_code(0x21)
/* find fsp in cbfs */
lea fsp_name, %esi
@@ -43,8 +41,7 @@
mov CBFS_FILE_OFFSET(%eax), %ebx
bswap %ebx
add %eax, %ebx
-
- addl $FSP_HDR_OFFSET, %ebx
+ add $0x94, %ebx
/*
* save mm2 into ebp, because TempRamInit API doesn't preserve
@@ -72,8 +69,7 @@
* If the TempRamInit API is successful, then when returning, the ECX and
* EDX registers will point to the temporary but writeable memory range
* available to the bootloader where ECX is the start and EDX is the end of
- * the range i.e. [ECX,EDX). See Denverton_ns FSP Integration Guide for more
- * information.
+ * the range i.e. [ECX,EDX). See FSP Integration Guide for more information.
*
* Return Values:
* EAX | Return Status
@@ -86,22 +82,22 @@
cmp $0, %eax
jnz .halt_forever
+ /* Setup bootblock stack */
+ mov %edx, %esp
+
/* clear CAR_GLOBAL area as it is not shared */
cld
- xor %eax, %eax
- movl $(_car_global_end), %ecx
- movl $(_car_global_start), %edi
- sub %edi, %ecx
+ xor %eax, %eax
+ movl $(_car_global_end), %ecx
+ movl $(_car_global_start), %edi
+ sub %edi, %ecx
shrl $2, %ecx
- rep stosl
-
- /* Setup bootblock stack */
- movl $(_car_stack_end), %esp
+ rep stosl
/* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */
push %ebp
- movd %mm1, %eax
- push %eax
+ movd %mm1, %eax
+ push %eax
/* We can call into C functions now */
call bootblock_c_entry
@@ -113,10 +109,9 @@
hlt
jmp .halt_forever
- .align 4
CAR_init_stack:
.long CAR_init_done
.long temp_ram_init_params
fsp_name:
- .ascii "fspt.bin\x00"
+ .string "fspt.bin\x00"
diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S
similarity index 68%
rename from src/soc/intel/apollolake/exit_car_fsp.S
rename to src/soc/intel/common/block/cpu/car/exit_car_fsp.S
index fbf2d31..4ac580c 100644
--- a/src/soc/intel/apollolake/exit_car_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -23,16 +23,8 @@
* the rest of arch/x86/exit_car.S and calls main() itself instead of
* returning to _start. In main(), the TempRamExit FSP API is called
* to tear down the CAR and set up caching which can be overwritten
- * after the API call. More info can be found in the Apollo Lake FSP
- * Integration Guide included with the FSP binary. The below
- * caching settings are based on an 8MiB Flash Size given as a
- * parameter to TempRamInit.
- *
- * TempRamExit MTRR Settings:
- * 0x00000000 - 0x0009FFFF | Write Back
- * 0x000C0000 - Top of Low Memory | Write Back
- * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect
- * 0x100000000 - Top of High Memory | Write Back
+ * after the API call. More info can be found in the FSP Integration
+ * Guide included with the FSP binary.
*/
.text
diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc
index 3f6333d..c024c3a 100644
--- a/src/soc/intel/denverton_ns/Makefile.inc
+++ b/src/soc/intel/denverton_ns/Makefile.inc
@@ -23,7 +23,6 @@
subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/x86/cache
-bootblock-$(CONFIG_FSP_CAR)+= bootblock/cache_as_ram_fsp.S
bootblock-y += bootblock/bootblock.c
bootblock-y += spi.c
bootblock-y += tsc_freq.c
@@ -31,7 +30,6 @@
bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
postcar-y += memmap.c
-postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
postcar-y += spi.c
postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c
diff --git a/src/soc/intel/denverton_ns/exit_car_fsp.S b/src/soc/intel/denverton_ns/exit_car_fsp.S
deleted file mode 100644
index 83d5a33..0000000
--- a/src/soc/intel/denverton_ns/exit_car_fsp.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016-2017 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cr.h>
-//#include <soc/cpu.h>
-
-/*
- * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
- * This version of chipset_teardown_car sets up the stack, then bypasses
- * the rest of arch/x86/exit_car.S and calls main() itself instead of
- * returning to _start. In main(), the TempRamExit FSP API is called
- * to tear down the CAR and set up caching which can be overwritten
- * after the API call. More info can be found in the Denverton-NS FSP
- * Integration Guide included with the FSP binary. The below
- * caching settings are based on an 8MiB Flash Size given as a
- * parameter to TempRamInit.
- *
- * TempRamExit MTRR Settings:
- * 0x00000000 - 0x0009FFFF | Write Back
- * 0x000C0000 - Top of Low Memory | Write Back
- * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect
- * 0x100000000 - Top of High Memory | Write Back
- */
-
-.text
-.global chipset_teardown_car
-chipset_teardown_car:
-
- /* Set up new stack. */
- mov post_car_stack_top, %esp
-
- /* Call C code */
- call main
--
To view, visit https://review.coreboot.org/29209
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Gerrit-Change-Number: 29209
Gerrit-PatchSet: 1
Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181022/56aa2e73/attachment-0001.html>
More information about the coreboot-gerrit
mailing list