<p>PraveenX Hodagatta Pranesh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29209">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel: Consolidate FSP CAR setup and teardown code<br><br>This patch adds following changes,<br><br>- APL, CFL, DENVERTON soc's using same implementation to setup and<br> teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is<br> cosolidated into one file and moved to common code CPU car folder.<br>- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file<br> and moved to common CPU car.<br>- Tempraminit parameters are passed from soc bootblock.c.<br><br>- Coffee lake Soc uses FSPT to support Intel Security features like<br> BootGuard verify boot and Measured boot. Add FSP CAR support for CFL<br> by programming tempraminit parameters and add FSP_T_XIP default if<br> FSP_CAR is selected.<br><br>BUG= None<br>TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.<br> Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR<br> without errors.<br><br>Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9<br>Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com><br>---<br>M src/soc/intel/apollolake/Makefile.inc<br>M src/soc/intel/apollolake/bootblock/bootblock.c<br>D src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/bootblock/bootblock.c<br>M src/soc/intel/common/block/cpu/Makefile.inc<br>R src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S<br>R src/soc/intel/common/block/cpu/car/exit_car_fsp.S<br>M src/soc/intel/denverton_ns/Makefile.inc<br>D src/soc/intel/denverton_ns/exit_car_fsp.S<br>10 files changed, 61 insertions(+), 196 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29209/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc</span><br><span>index 632cb99..d2a9a1f 100644</span><br><span>--- a/src/soc/intel/apollolake/Makefile.inc</span><br><span>+++ b/src/soc/intel/apollolake/Makefile.inc</span><br><span>@@ -18,7 +18,6 @@</span><br><span> bootblock-y += pmutil.c</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S</span><br><span> </span><br><span> romstage-y += car.c</span><br><span> romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c</span><br><span>@@ -74,8 +73,6 @@</span><br><span> postcar-y += i2c.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> verstage-y += car.c</span><br><span> verstage-y += i2c.c</span><br><span> verstage-y += gspi.c</span><br><span>diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>index bc5c170..0ec80a0 100644</span><br><span>--- a/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016-2018 Intel Corp.</span><br><span> * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span>@@ -34,6 +34,25 @@</span><br><span> #include <soc/pm.h></span><br><span> #include <spi-generic.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <FsptUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const FSPT_UPD temp_ram_init_params = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .FspUpdHeader = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .Signature = 0x545F4450554C5041ULL, /* 'APLUPD_T' */</span><br><span style="color: hsl(120, 100%, 40%);">+ .Revision = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .Reserved = {0},</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .FsptCommonUpd = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .Revision = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .Reserved = {0},</span><br><span style="color: hsl(120, 100%, 40%);">+ .MicrocodeRegionBase = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .MicrocodeRegionLength = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .CodeRegionBase =</span><br><span style="color: hsl(120, 100%, 40%);">+ (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),</span><br><span style="color: hsl(120, 100%, 40%);">+ .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .Reserved1 = {0},</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span> </span><br><span> static const struct pad_config tpm_spi_configs[] = {</span><br><span> #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)</span><br><span>diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S</span><br><span>deleted file mode 100644</span><br><span>index 4c4fa71..0000000</span><br><span>--- a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S</span><br><span>+++ /dev/null</span><br><span>@@ -1,110 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015-2016 Intel Corp.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(0, 100%, 40%);">- * (at your option) any later version.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cache.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/post_code.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <../../../arch/x86/walkcbfs.S></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define FSP_HDR_OFFSET 0x94</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.global bootblock_pre_c_entry</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock_pre_c_entry:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.global cache_as_ram</span><br><span style="color: hsl(0, 100%, 40%);">-cache_as_ram:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x21)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* find fsp in cbfs */</span><br><span style="color: hsl(0, 100%, 40%);">- lea fsp_name, %esi</span><br><span style="color: hsl(0, 100%, 40%);">- mov $1f, %esp</span><br><span style="color: hsl(0, 100%, 40%);">- jmp walkcbfs_asm</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- cmp $0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- jz .halt_forever</span><br><span style="color: hsl(0, 100%, 40%);">- mov CBFS_FILE_OFFSET(%eax), %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- bswap %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- add %eax, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- add FSP_HDR_OFFSET, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * ebx = FSP INFO HEADER</span><br><span style="color: hsl(0, 100%, 40%);">- * Calculate entry into FSP</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */</span><br><span style="color: hsl(0, 100%, 40%);">- add 0x1c(%ebx), %eax /* add the FSP ImageBase */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Pass early init variables on a fake stack (no memory yet)</span><br><span style="color: hsl(0, 100%, 40%);">- * as well as the return location</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- lea CAR_init_stack, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* call FSP binary to setup temporary stack */</span><br><span style="color: hsl(0, 100%, 40%);">- jmp *%eax</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * If the TempRamInit API is successful, then when returning, the ECX and</span><br><span style="color: hsl(0, 100%, 40%);">- * EDX registers will point to the temporary but writeable memory range</span><br><span style="color: hsl(0, 100%, 40%);">- * available to the bootloader where ECX is the start and EDX is the end of</span><br><span style="color: hsl(0, 100%, 40%);">- * the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more</span><br><span style="color: hsl(0, 100%, 40%);">- * information.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Return Values:</span><br><span style="color: hsl(0, 100%, 40%);">- * EAX | Return Status</span><br><span style="color: hsl(0, 100%, 40%);">- * ECX | Temporary Memory Start</span><br><span style="color: hsl(0, 100%, 40%);">- * EDX | Temporary Memory End</span><br><span style="color: hsl(0, 100%, 40%);">- * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-CAR_init_done:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup bootblock stack */</span><br><span style="color: hsl(0, 100%, 40%);">- mov %edx, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* clear CAR_GLOBAL area as it is not shared */</span><br><span style="color: hsl(0, 100%, 40%);">- cld</span><br><span style="color: hsl(0, 100%, 40%);">- xor %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(_car_global_end), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(_car_global_start), %edi</span><br><span style="color: hsl(0, 100%, 40%);">- sub %edi, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rep stosl</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We can call into C functions now */</span><br><span style="color: hsl(0, 100%, 40%);">- call bootblock_c_entry</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Never reached */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.halt_forever:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_DEAD_CODE)</span><br><span style="color: hsl(0, 100%, 40%);">- hlt</span><br><span style="color: hsl(0, 100%, 40%);">- jmp .halt_forever</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-CAR_init_params:</span><br><span style="color: hsl(0, 100%, 40%);">- .long 0 /* Microcode Location */</span><br><span style="color: hsl(0, 100%, 40%);">- .long 0 /* Microcode Length */</span><br><span style="color: hsl(0, 100%, 40%);">- .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */</span><br><span style="color: hsl(0, 100%, 40%);">- .long CONFIG_ROM_SIZE /* Total Firmware Length */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-CAR_init_stack:</span><br><span style="color: hsl(0, 100%, 40%);">- .long CAR_init_done</span><br><span style="color: hsl(0, 100%, 40%);">- .long CAR_init_params</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-fsp_name:</span><br><span style="color: hsl(0, 100%, 40%);">- .ascii "blobs/fspt.bin\x00"</span><br><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index abe029a..161db33 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -75,6 +75,7 @@</span><br><span> select UDELAY_TSC</span><br><span> select UDK_2017_BINDING</span><br><span> select DISPLAY_FSP_VERSION_INFO</span><br><span style="color: hsl(120, 100%, 40%);">+ select FSP_T_XIP if FSP_CAR</span><br><span> </span><br><span> config UART_DEBUG</span><br><span> bool "Enable UART debug port."</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c</span><br><span>index 0aac186..805ae0e 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation..</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Intel Corporation..</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -19,6 +19,24 @@</span><br><span> #include <soc/bootblock.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <FsptUpd.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const FSPT_UPD temp_ram_init_params = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .FspUpdHeader = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .Signature = 0x545F4450554C4643ULL, /* 'CFLUPD_T' */</span><br><span style="color: hsl(120, 100%, 40%);">+ .Revision = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .Reserved = {0},</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .FsptCoreUpd = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .MicrocodeRegionBase =</span><br><span style="color: hsl(120, 100%, 40%);">+ (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,</span><br><span style="color: hsl(120, 100%, 40%);">+ .MicrocodeRegionSize =</span><br><span style="color: hsl(120, 100%, 40%);">+ (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,</span><br><span style="color: hsl(120, 100%, 40%);">+ .CodeRegionBase =</span><br><span style="color: hsl(120, 100%, 40%);">+ (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),</span><br><span style="color: hsl(120, 100%, 40%);">+ .CodeRegionSize = (UINT32)CONFIG_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span> </span><br><span> asmlinkage void bootblock_c_entry(uint64_t base_timestamp)</span><br><span> {</span><br><span>diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc</span><br><span>index aa61ffc..5207227 100644</span><br><span>--- a/src/soc/intel/common/block/cpu/Makefile.inc</span><br><span>+++ b/src/soc/intel/common/block/cpu/Makefile.inc</span><br><span>@@ -1,10 +1,12 @@</span><br><span> bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S</span><br><span> bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S</span><br><span> romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c</span><br><span> </span><br><span> postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S</span><br><span> </span><br><span> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c</span><br><span> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c</span><br><span>diff --git a/src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S</span><br><span>similarity index 82%</span><br><span>rename from src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S</span><br><span>rename to src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S</span><br><span>index b998c21..5bab9cd 100644</span><br><span>--- a/src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S</span><br><span>+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2015 - 2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -19,10 +19,8 @@</span><br><span> #include <cpu/x86/cache.h></span><br><span> #include <cpu/x86/cr.h></span><br><span> #include <cpu/x86/post_code.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <../../../../../arch/x86/walkcbfs.S></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <../../../arch/x86/walkcbfs.S></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define FSP_HDR_OFFSET 0x94</span><br><span> </span><br><span> .extern temp_ram_init_params</span><br><span> </span><br><span>@@ -31,7 +29,7 @@</span><br><span> </span><br><span> .global cache_as_ram</span><br><span> cache_as_ram:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x2f)</span><br><span style="color: hsl(120, 100%, 40%);">+ post_code(0x21)</span><br><span> </span><br><span> /* find fsp in cbfs */</span><br><span> lea fsp_name, %esi</span><br><span>@@ -43,8 +41,7 @@</span><br><span> mov CBFS_FILE_OFFSET(%eax), %ebx</span><br><span> bswap %ebx</span><br><span> add %eax, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- addl $FSP_HDR_OFFSET, %ebx</span><br><span style="color: hsl(120, 100%, 40%);">+ add $0x94, %ebx</span><br><span> </span><br><span> /*</span><br><span> * save mm2 into ebp, because TempRamInit API doesn't preserve</span><br><span>@@ -72,8 +69,7 @@</span><br><span> * If the TempRamInit API is successful, then when returning, the ECX and</span><br><span> * EDX registers will point to the temporary but writeable memory range</span><br><span> * available to the bootloader where ECX is the start and EDX is the end of</span><br><span style="color: hsl(0, 100%, 40%);">- * the range i.e. [ECX,EDX). See Denverton_ns FSP Integration Guide for more</span><br><span style="color: hsl(0, 100%, 40%);">- * information.</span><br><span style="color: hsl(120, 100%, 40%);">+ * the range i.e. [ECX,EDX). See FSP Integration Guide for more information.</span><br><span> *</span><br><span> * Return Values:</span><br><span> * EAX | Return Status</span><br><span>@@ -86,22 +82,22 @@</span><br><span> cmp $0, %eax</span><br><span> jnz .halt_forever</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Setup bootblock stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ mov %edx, %esp</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* clear CAR_GLOBAL area as it is not shared */</span><br><span> cld</span><br><span style="color: hsl(0, 100%, 40%);">- xor %eax, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(_car_global_end), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(_car_global_start), %edi</span><br><span style="color: hsl(0, 100%, 40%);">- sub %edi, %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ xor %eax, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(_car_global_end), %ecx</span><br><span style="color: hsl(120, 100%, 40%);">+ movl $(_car_global_start), %edi</span><br><span style="color: hsl(120, 100%, 40%);">+ sub %edi, %ecx</span><br><span> shrl $2, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rep stosl</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Setup bootblock stack */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $(_car_stack_end), %esp</span><br><span style="color: hsl(120, 100%, 40%);">+ rep stosl</span><br><span> </span><br><span> /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */</span><br><span> push %ebp</span><br><span style="color: hsl(0, 100%, 40%);">- movd %mm1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- push %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ movd %mm1, %eax</span><br><span style="color: hsl(120, 100%, 40%);">+ push %eax</span><br><span> </span><br><span> /* We can call into C functions now */</span><br><span> call bootblock_c_entry</span><br><span>@@ -113,10 +109,9 @@</span><br><span> hlt</span><br><span> jmp .halt_forever</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- .align 4</span><br><span> CAR_init_stack:</span><br><span> .long CAR_init_done</span><br><span> .long temp_ram_init_params</span><br><span> </span><br><span> fsp_name:</span><br><span style="color: hsl(0, 100%, 40%);">- .ascii "fspt.bin\x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ .string "fspt.bin\x00"</span><br><span>diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S</span><br><span>similarity index 68%</span><br><span>rename from src/soc/intel/apollolake/exit_car_fsp.S</span><br><span>rename to src/soc/intel/common/block/cpu/car/exit_car_fsp.S</span><br><span>index fbf2d31..4ac580c 100644</span><br><span>--- a/src/soc/intel/apollolake/exit_car_fsp.S</span><br><span>+++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corp.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or</span><br><span> * modify it under the terms of the GNU General Public License as</span><br><span>@@ -23,16 +23,8 @@</span><br><span> * the rest of arch/x86/exit_car.S and calls main() itself instead of</span><br><span> * returning to _start. In main(), the TempRamExit FSP API is called</span><br><span> * to tear down the CAR and set up caching which can be overwritten</span><br><span style="color: hsl(0, 100%, 40%);">- * after the API call. More info can be found in the Apollo Lake FSP</span><br><span style="color: hsl(0, 100%, 40%);">- * Integration Guide included with the FSP binary. The below</span><br><span style="color: hsl(0, 100%, 40%);">- * caching settings are based on an 8MiB Flash Size given as a</span><br><span style="color: hsl(0, 100%, 40%);">- * parameter to TempRamInit.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * TempRamExit MTRR Settings:</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x00000000 - 0x0009FFFF | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x000C0000 - Top of Low Memory | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x100000000 - Top of High Memory | Write Back</span><br><span style="color: hsl(120, 100%, 40%);">+ * after the API call. More info can be found in the FSP Integration</span><br><span style="color: hsl(120, 100%, 40%);">+ * Guide included with the FSP binary.</span><br><span> */</span><br><span> </span><br><span> .text</span><br><span>diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc</span><br><span>index 3f6333d..c024c3a 100644</span><br><span>--- a/src/soc/intel/denverton_ns/Makefile.inc</span><br><span>+++ b/src/soc/intel/denverton_ns/Makefile.inc</span><br><span>@@ -23,7 +23,6 @@</span><br><span> subdirs-y += ../../../cpu/x86/tsc</span><br><span> subdirs-y += ../../../cpu/x86/cache</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-$(CONFIG_FSP_CAR)+= bootblock/cache_as_ram_fsp.S</span><br><span> bootblock-y += bootblock/bootblock.c</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += tsc_freq.c</span><br><span>@@ -31,7 +30,6 @@</span><br><span> bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c</span><br><span> </span><br><span> postcar-y += memmap.c</span><br><span style="color: hsl(0, 100%, 40%);">-postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S</span><br><span> postcar-y += spi.c</span><br><span> postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c</span><br><span> </span><br><span>diff --git a/src/soc/intel/denverton_ns/exit_car_fsp.S b/src/soc/intel/denverton_ns/exit_car_fsp.S</span><br><span>deleted file mode 100644</span><br><span>index 83d5a33..0000000</span><br><span>--- a/src/soc/intel/denverton_ns/exit_car_fsp.S</span><br><span>+++ /dev/null</span><br><span>@@ -1,47 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016-2017 Intel Corp.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(0, 100%, 40%);">- * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(0, 100%, 40%);">- * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(0, 100%, 40%);">- * the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <cpu/x86/cr.h></span><br><span style="color: hsl(0, 100%, 40%);">-//#include <soc/cpu.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.</span><br><span style="color: hsl(0, 100%, 40%);">- * This version of chipset_teardown_car sets up the stack, then bypasses</span><br><span style="color: hsl(0, 100%, 40%);">- * the rest of arch/x86/exit_car.S and calls main() itself instead of</span><br><span style="color: hsl(0, 100%, 40%);">- * returning to _start. In main(), the TempRamExit FSP API is called</span><br><span style="color: hsl(0, 100%, 40%);">- * to tear down the CAR and set up caching which can be overwritten</span><br><span style="color: hsl(0, 100%, 40%);">- * after the API call. More info can be found in the Denverton-NS FSP</span><br><span style="color: hsl(0, 100%, 40%);">- * Integration Guide included with the FSP binary. The below</span><br><span style="color: hsl(0, 100%, 40%);">- * caching settings are based on an 8MiB Flash Size given as a</span><br><span style="color: hsl(0, 100%, 40%);">- * parameter to TempRamInit.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * TempRamExit MTRR Settings:</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x00000000 - 0x0009FFFF | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x000C0000 - Top of Low Memory | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x100000000 - Top of High Memory | Write Back</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-.text</span><br><span style="color: hsl(0, 100%, 40%);">-.global chipset_teardown_car</span><br><span style="color: hsl(0, 100%, 40%);">-chipset_teardown_car:</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set up new stack. */</span><br><span style="color: hsl(0, 100%, 40%);">- mov post_car_stack_top, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Call C code */</span><br><span style="color: hsl(0, 100%, 40%);">- call main</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29209">change 29209</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
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<div style="display:none"> Gerrit-Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 </div>
<div style="display:none"> Gerrit-Change-Number: 29209 </div>
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<div style="display:none"> Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> </div>