[coreboot-gerrit] Change in coreboot[master]: mb/google/fizz/variants/kalista: Add variant for kalista
David Wu (Code Review)
gerrit at coreboot.org
Mon Oct 22 04:28:17 CEST 2018
David Wu has uploaded this change for review. ( https://review.coreboot.org/29205
Change subject: mb/google/fizz/variants/kalista: Add variant for kalista
......................................................................
mb/google/fizz/variants/kalista: Add variant for kalista
Add a new variant of fizz for the kalista board.
Key differences from baseboard include:
- GPIO changes
- devicetree.cb changes
BUG=b:117066935
BRANCH=master
TEST=Build (as initial setup)
Change-Id: I808c5e0883049575cbedd181c249a78a833fa96a
Signed-off-by: David Wu <David_Wu at quanta.corp-partner.google.com>
---
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/fizz/Kconfig.name
A src/mainboard/google/fizz/variants/kalista/Makefile.inc
A src/mainboard/google/fizz/variants/kalista/devicetree.cb
A src/mainboard/google/fizz/variants/kalista/gpio.c
A src/mainboard/google/fizz/variants/kalista/include/variant/acpi/dptf.asl
A src/mainboard/google/fizz/variants/kalista/include/variant/ec.h
A src/mainboard/google/fizz/variants/kalista/include/variant/gpio.h
A src/mainboard/google/fizz/variants/kalista/nhlt.c
9 files changed, 911 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29205/1
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 6ab94c9..a98d125 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -2,6 +2,8 @@
config BOARD_GOOGLE_BASEBOARD_FIZZ
def_bool n
select BOARD_ROMSIZE_KB_16384
+ select DRIVERS_GENERIC_MAX98357A if BOARD_GOOGLE_KALISTA
+ select DRIVERS_I2C_DA7219 if BOARD_GOOGLE_KALISTA
select DRIVERS_I2C_GENERIC
select DRIVERS_SPI_ACPI
select DRIVERS_USB_ACPI
@@ -27,6 +29,7 @@
config DEVICETREE
string
+ default "variants/kalista/devicetree.cb" if BOARD_GOOGLE_KALISTA
default "variants/baseboard/devicetree.cb"
config VBOOT
@@ -43,6 +46,7 @@
string
depends on CHROMEOS
default "FIZZ TEST 5997" if BOARD_GOOGLE_FIZZ
+ default "KALISTA TEST 0932" if BOARD_GOOGLE_KALISTA
config MAINBOARD_DIR
string
@@ -51,10 +55,12 @@
config MAINBOARD_PART_NUMBER
string
default "Fizz" if BOARD_GOOGLE_FIZZ
+ default "Kalista" if BOARD_GOOGLE_KALISTA
config MAINBOARD_FAMILY
string
default "Google_Fizz" if BOARD_GOOGLE_FIZZ
+ default "Google_Kalista" if BOARD_GOOGLE_KALISTA
config MAX_CPUS
int
@@ -75,9 +81,16 @@
config VARIANT_DIR
string
default "fizz" if BOARD_GOOGLE_FIZZ
+ default "kalista" if BOARD_GOOGLE_KALISTA
config INCLUDE_NHLT_BLOBS
bool "Include blobs for audio."
select NHLT_RT5663
+config INCLUDE_NHLT_BLOBS_KALISTA
+ bool "Include blobs for kalista audio."
+ select NHLT_DA7219
+ select NHLT_DMIC_4CH
+ select NHLT_MAX98357
+
endif # BOARD_GOOGLE_BASEBOARD_FIZZ
diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name
index 28c9700..2911b21 100644
--- a/src/mainboard/google/fizz/Kconfig.name
+++ b/src/mainboard/google/fizz/Kconfig.name
@@ -1,3 +1,7 @@
config BOARD_GOOGLE_FIZZ
bool "Fizz"
select BOARD_GOOGLE_BASEBOARD_FIZZ
+
+config BOARD_GOOGLE_KALISTA
+ bool "Kalista"
+ select BOARD_GOOGLE_BASEBOARD_FIZZ
diff --git a/src/mainboard/google/fizz/variants/kalista/Makefile.inc b/src/mainboard/google/fizz/variants/kalista/Makefile.inc
new file mode 100644
index 0000000..0ad298b
--- /dev/null
+++ b/src/mainboard/google/fizz/variants/kalista/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+ramstage-y += nhlt.c
diff --git a/src/mainboard/google/fizz/variants/kalista/devicetree.cb b/src/mainboard/google/fizz/variants/kalista/devicetree.cb
new file mode 100644
index 0000000..c563b0d
--- /dev/null
+++ b/src/mainboard/google/fizz/variants/kalista/devicetree.cb
@@ -0,0 +1,510 @@
+chip soc/intel/skylake
+
+ # Deep Sx states
+ register "deep_s3_enable_ac" = "0"
+ register "deep_s3_enable_dc" = "0"
+ register "deep_s5_enable_ac" = "1"
+ register "deep_s5_enable_dc" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
+
+ # Mapping of USB port # to device
+ #+----------------+-------+-----------------------------------+
+ #| Device | Port# | Rev |
+ #+----------------+-------+-----------------------------------+
+ #| USB C | 1 | 2/3 |
+ #| USB A Rear | 2 | 2/3 |
+ #| USB A Front | 3 | 2/3 |
+ #| USB A Front | 4 | 2/3 |
+ #| USB A Rear | 5 | 2 on base celeron, 2/3 all others |
+ #| USB A Rear | 6 | 2 on base celeron, 2/3 all others |
+ #| Bluetooth | 7 | |
+ #| Daughter Board | 8 | |
+ #| Touchsreen | 10 | |
+ #+----------------+-------+-----------------------------------+
+
+ # Bitmap for Wake Enable on USB attach/detach
+ register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(4) | \
+ USB_PORT_WAKE_ENABLE(5) | \
+ USB_PORT_WAKE_ENABLE(6)"
+ register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(4) | \
+ USB_PORT_WAKE_ENABLE(5) | \
+ USB_PORT_WAKE_ENABLE(6)"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[1]" = "1"
+ register "SataPwrOptEnable" = "1"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "EnableTraceHub" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "2"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
+ register "SendVrMbxCmd" = "1" # IMVP8 workaround
+ register "VmxEnable" = "1"
+
+ # Intersil VR c-state issue workaround
+ # send VR mailbox command for IA/GT/SA rails
+ register "IslVrCmd" = "2"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
+ #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |
+ #+----------------+-------+-------+-------+-------+
+ #Note: IccMax settings are moved to SoC code
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ .ac_loadline = 1030,
+ .dc_loadline = 1030,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ .ac_loadline = 240,
+ .dc_loadline = 240,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ .ac_loadline = 310,
+ .dc_loadline = 310,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .voltage_limit = 1520,
+ .ac_loadline = 310,
+ .dc_loadline = 310,
+ }"
+
+ # Enable Root port 3(x1) for LAN.
+ register "PcieRpEnable[2]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[2]" = "1"
+ # RP 3 uses SRCCLKREQ0#
+ register "PcieRpClkReqNumber[2]" = "0"
+ # RP 3, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[2]" = "1"
+ # RP 3, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[2]" = "1"
+ # RP 3 uses uses CLK SRC 0
+ register "PcieRpClkSrcNumber[2]" = "0"
+
+ # Enable Root port 4(x1) for WLAN.
+ register "PcieRpEnable[3]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[3]" = "1"
+ # RP 4 uses SRCCLKREQ5#
+ register "PcieRpClkReqNumber[3]" = "5"
+ # RP 4, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[3]" = "1"
+ # RP 4, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[3]" = "1"
+ # RP 4 uses uses CLK SRC 5
+ register "PcieRpClkSrcNumber[3]" = "5"
+
+ # Enable Root port 5(x4) for NVMe.
+ register "PcieRpEnable[4]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[4]" = "1"
+ # RP 5 uses SRCCLKREQ1#
+ register "PcieRpClkReqNumber[4]" = "1"
+ # RP 5, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ # RP 5, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[4]" = "1"
+ # RP 5 uses CLK SRC 1
+ register "PcieRpClkSrcNumber[4]" = "1"
+
+ # Enable Root port 9 for BtoB.
+ register "PcieRpEnable[8]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[8]" = "1"
+ # RP 9 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[8]" = "2"
+ # RP 9, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ # RP 9, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[8]" = "1"
+ # RP 9 uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[8]" = "2"
+
+ # Enable Root port 11 for BtoB.
+ register "PcieRpEnable[10]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[10]" = "1"
+ # RP 11 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[10]" = "2"
+ # RP 11, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[10]" = "1"
+ # RP 11, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[10]" = "1"
+ # RP 11 uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[10]" = "2"
+
+ # Enable Root port 12 for BtoB.
+ register "PcieRpEnable[11]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[11]" = "1"
+ # RP 12 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[11]" = "2"
+ # RP 12, Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[11]" = "1"
+ # RP 12, Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[11]" = "1"
+ # RP 12 uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[11]" = "2"
+
+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected)
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear
+
+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC
+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM
+ register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug
+ register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C5 | Audio |
+ #+-------------------+---------------------------+
+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 194,
+ .scl_hcnt = 100,
+ .sda_hold = 36,
+ },
+ },
+ }"
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexSpi0] = PchSerialIoPci,
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart0] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
+ }"
+
+ register "speed_shift_enable" = "1"
+ register "tdp_psyspl2" = "90"
+ register "psys_pmax" = "120"
+ register "tcc_offset" = "6" # TCC of 94C
+
+ # Use default SD card detect GPIO configuration
+ register "sdcard_cd_gpio_default" = "GPP_A7"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Rear""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device usb 2.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Left""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Front Right""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Front Left""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Right""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Rear Middle""
+ register "type" = "UPC_TYPE_A"
+ device usb 2.5 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Touchscreen""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Rear""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ device usb 3.0 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Left""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Front Right""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Front Left""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Right""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Rear Middle""
+ register "type" = "UPC_TYPE_USB3_A"
+ device usb 3.5 on end
+ end
+ end
+ end
+ end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
+ register "sdmode_delay" = "5"
+ device generic 0 on end
+ end
+ chip drivers/i2c/da7219
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)"
+ register "btn_cfg" = "50"
+ register "mic_det_thr" = "500"
+ register "jack_ins_deb" = "20"
+ register "jack_det_rate" = ""32ms_64ms""
+ register "jack_rem_deb" = "1"
+ register "a_d_btn_thr" = "0xa"
+ register "d_b_btn_thr" = "0x16"
+ register "b_c_btn_thr" = "0x21"
+ register "c_mic_btn_thr" = "0x3e"
+ register "btn_avg" = "4"
+ register "adc_1bit_rpt" = "1"
+ register "micbias_lvl" = "2600"
+ register "mic_amp_in_sel" = ""diff""
+ device i2c 1a on end
+ end
+ end # I2C #5
+ device pci 19.2 off end # I2C #4
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP
+ device pci 1c.2 on
+ chip drivers/net
+ register "customized_leds" = "0x0fa5"
+ register "wake" = "GPE0_PCI_EXP"
+ register "device_index" = "1"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 3
+ device pci 1c.3 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_PCI_EXP"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 4 for WLAN
+ device pci 1c.4 on end # PCI Express Port 5 for NVMe
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on # PCI Express Port 9 for 2nd LAN
+ chip drivers/net
+ register "customized_leds" = "0x0fa5"
+ register "device_index" = "2"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 9 for BtoB
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 on end # PCI Express Port 11
+ device pci 1d.3 on end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 on
+ chip drivers/spi/acpi
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "compat_string" = ""google,cr50""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
+ device spi 0 on end
+ end
+ end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 off end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 on end # SDCard
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/google/fizz/variants/kalista/gpio.c b/src/mainboard/google/fizz/variants/kalista/gpio.c
new file mode 100644
index 0000000..98231d8
--- /dev/null
+++ b/src/mainboard/google/fizz/variants/kalista/gpio.c
@@ -0,0 +1,278 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */
+/* ESPI_IO0 */
+/* ESPI_IO1 */
+/* ESPI_IO2 */
+/* ESPI_IO3 */
+/* ESPI_CS# */
+/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */
+/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP,
+ EDGE), /* SD_CDZ */
+/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */
+/* ESPI_CLK */
+/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */
+/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */
+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
+/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,
+ DEEP), /* eSPI mode */
+/* ESPI_RESET# */
+/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */
+/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */
+/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */
+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_SPK_EN */
+
+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */
+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
+/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */
+/* CPU_GP2 */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* TOUCHSCREEN_RST# */
+/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* PCH_TS_EN */
+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP,
+ NF1), /* CLK_PCIE_LAN_REQ# */
+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP,
+ NF1), /* PCIE_CLKREQ_SSD# */
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP,
+ NF1), /* PCIE_CLKREQ_NGFF1# */
+/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */
+/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */
+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP,
+ NF1), /* PCIE_CLKREQ_WLAN# */
+/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */
+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */
+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */
+/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */
+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_CS_L */
+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_CLK */
+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_MISO */
+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_MOSI */
+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */
+/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU,
+ DEEP), /* VR_DISABLE_L */
+/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU,
+ DEEP), /* HWA_TRST_N */
+/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */
+/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */
+
+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */
+/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */
+/* SMBALERT# */ PAD_CFG_NC(GPP_C2),
+/* SML0CLK */ PAD_CFG_NC(GPP_C3),
+/* SML0DATA */ PAD_CFG_NC(GPP_C4),
+/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,
+ DEEP), /* EC_IN_RW */
+/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */
+/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU,
+ DEEP), /* GPIO1 */
+/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU,
+ DEEP), /* GPIO2 */
+/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* V3P3_CCD_EN */
+/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU,
+ DEEP), /* GPIO4 */
+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
+ DEEP), /* SKU_ID0 */
+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
+ DEEP), /* SKU_ID1 */
+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
+ DEEP), /* SKU_ID2 */
+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
+ DEEP), /* SKU_ID3 */
+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+/* I2C1_SDA */ PAD_CFG_NC(GPP_C18),
+/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),
+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
+/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */
+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
+ DEEP), /* SCREW_SPI_WP_STATUS */
+
+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */
+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */
+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */
+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */
+/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */
+/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCH_I2C0_8625_SDA */
+/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCH_I2C0_8625_SCL */
+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
+/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE,
+ PLTRST, EDGE), /* HP_IRQ_GPIO */
+/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE,
+ DEEP), /* OEM_ID1 */
+/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE,
+ DEEP), /* OEM_ID2 */
+/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE,
+ DEEP), /* OEM_ID3 */
+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
+/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
+/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* PCH_DMIC_CLK0 */
+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* PCH_DMIC_DATA0 */
+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */
+/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* BOOT_BEEP_OVERRIDE */
+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */
+
+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
+ PLTRST), /* H1_PCH_INT_ODL */
+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,
+ NF1), /* MB_PCIE_SATA#_DET */
+/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,
+ NF1), /* DB_PCIE_SATA#_DET */
+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
+/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */
+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */
+/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT# */
+/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */
+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */
+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP,
+ NF1), /* Rear Dual-Stack USB Ports */
+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,
+ NF1), /* Front USB Ports */
+/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,
+ NF1), /* Rear Single USB Port */
+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,
+ NF1), /* INT_HDMI_HPD */
+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,
+ NF1), /* DDI2_HPD */
+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */
+/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */
+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP,
+ NF1), /* HDMI_DDCCLK_SW */
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP,
+ NF1), /* HDMI_DDCCLK_DATA */
+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */
+/* DDPD_CTRLCLK */ PAD_CFG_GPO(GPP_E22, 1, DEEP), /* DP_RST_L */
+/* DDPD_CTRLDATA */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* DP_PD_L */
+
+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S_2_BCLK */
+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S_2_FS_LRC */
+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_2_TX_DAC */
+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */
+/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP,
+ NF1), /* PCH_I2C2_H1_3V3_SDA */
+/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP,
+ NF1), /* PCH_I2C2_H1_3V3_SCL */
+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
+/* I2C4_SDA */ PAD_CFG_NC(GPP_F8),
+/* I2C4_SCL */ PAD_CFG_NC(GPP_F9),
+/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,
+ NF1), /* PCH_I2C2_AUDIO_1V8_SDA */
+/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,
+ NF1), /* PCH_I2C2_AUDIO_1V8_SCL */
+/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
+/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
+/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),
+/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),
+/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),
+/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),
+/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),
+/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),
+/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),
+/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),
+/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),
+/* RSVD */ PAD_CFG_NC(GPP_F23),
+
+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */
+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */
+
+/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */
+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */
+/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */
+/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */
+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */
+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */
+/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */
+/* RSVD */ PAD_CFG_NC(GPD7),
+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */
+/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */
+/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */
+/* LANPHYC */ PAD_CFG_NC(GPD11),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_CS_L */
+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_CLK */
+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_MISO */
+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
+ NF1), /* PCH_SPI_H1_3V3_MOSI */
+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
+ PLTRST), /* H1_PCH_INT_ODL */
+/* Ensure UART pins are in native mode for H1. */
+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
+ DEEP), /* SCREW_SPI_WP_STATUS */
+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,
+ NF1), /* MB_PCIE_SATA#_DET */
+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/google/fizz/variants/kalista/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/kalista/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..a9afa73
--- /dev/null
+++ b/src/mainboard/google/fizz/variants/kalista/include/variant/acpi/dptf.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/fizz/variants/kalista/include/variant/ec.h b/src/mainboard/google/fizz/variants/kalista/include/variant/ec.h
new file mode 100644
index 0000000..3d4fc8f
--- /dev/null
+++ b/src/mainboard/google/fizz/variants/kalista/include/variant/ec.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/fizz/variants/kalista/include/variant/gpio.h b/src/mainboard/google/fizz/variants/kalista/include/variant/gpio.h
new file mode 100644
index 0000000..cd34cf0
--- /dev/null
+++ b/src/mainboard/google/fizz/variants/kalista/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fizz/variants/kalista/nhlt.c b/src/mainboard/google/fizz/variants/kalista/nhlt.c
new file mode 100644
index 0000000..af02179
--- /dev/null
+++ b/src/mainboard/google/fizz/variants/kalista/nhlt.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <nhlt.h>
+#include <soc/nhlt.h>
+
+void variant_nhlt_init(struct nhlt *nhlt)
+{
+ /* 4 Channel DMIC array. */
+ if (nhlt_soc_add_dmic_array(nhlt, 4))
+ printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n");
+
+ /* Dialog DA7219 Headset codec. */
+ if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))
+ printk(BIOS_ERR, "Couldn't add Dialog DA7219.\n");
+
+ /* MAXIM Smart Amps for left and right speakers. */
+ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
+ printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n");
+
+}
+
+void variant_nhlt_oem_overrides(const char **oem_id,
+ const char **oem_table_id,
+ uint32_t *oem_revision)
+{
+ *oem_id = "GOOGLE";
+ *oem_table_id = "KALISTA";
+ *oem_revision = 0;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I808c5e0883049575cbedd181c249a78a833fa96a
Gerrit-Change-Number: 29205
Gerrit-PatchSet: 1
Gerrit-Owner: David Wu <david_wu at quanta.corp-partner.google.com>
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