<p>David Wu has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29205">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/fizz/variants/kalista: Add variant for kalista<br><br>Add a new variant of fizz for the kalista board.<br><br>Key differences from baseboard include:<br>- GPIO changes<br>- devicetree.cb changes<br><br>BUG=b:117066935<br>BRANCH=master<br>TEST=Build (as initial setup)<br><br>Change-Id: I808c5e0883049575cbedd181c249a78a833fa96a<br>Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com><br>---<br>M src/mainboard/google/fizz/Kconfig<br>M src/mainboard/google/fizz/Kconfig.name<br>A src/mainboard/google/fizz/variants/kalista/Makefile.inc<br>A src/mainboard/google/fizz/variants/kalista/devicetree.cb<br>A src/mainboard/google/fizz/variants/kalista/gpio.c<br>A src/mainboard/google/fizz/variants/kalista/include/variant/acpi/dptf.asl<br>A src/mainboard/google/fizz/variants/kalista/include/variant/ec.h<br>A src/mainboard/google/fizz/variants/kalista/include/variant/gpio.h<br>A src/mainboard/google/fizz/variants/kalista/nhlt.c<br>9 files changed, 911 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29205/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig</span><br><span>index 6ab94c9..a98d125 100644</span><br><span>--- a/src/mainboard/google/fizz/Kconfig</span><br><span>+++ b/src/mainboard/google/fizz/Kconfig</span><br><span>@@ -2,6 +2,8 @@</span><br><span> config BOARD_GOOGLE_BASEBOARD_FIZZ</span><br><span> def_bool n</span><br><span> select BOARD_ROMSIZE_KB_16384</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_GENERIC_MAX98357A if BOARD_GOOGLE_KALISTA</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_I2C_DA7219 if BOARD_GOOGLE_KALISTA</span><br><span> select DRIVERS_I2C_GENERIC</span><br><span> select DRIVERS_SPI_ACPI</span><br><span> select DRIVERS_USB_ACPI</span><br><span>@@ -27,6 +29,7 @@</span><br><span> </span><br><span> config DEVICETREE</span><br><span> string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/kalista/devicetree.cb" if BOARD_GOOGLE_KALISTA</span><br><span> default "variants/baseboard/devicetree.cb"</span><br><span> </span><br><span> config VBOOT</span><br><span>@@ -43,6 +46,7 @@</span><br><span> string</span><br><span> depends on CHROMEOS</span><br><span> default "FIZZ TEST 5997" if BOARD_GOOGLE_FIZZ</span><br><span style="color: hsl(120, 100%, 40%);">+ default "KALISTA TEST 0932" if BOARD_GOOGLE_KALISTA</span><br><span> </span><br><span> config MAINBOARD_DIR</span><br><span> string</span><br><span>@@ -51,10 +55,12 @@</span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span> default "Fizz" if BOARD_GOOGLE_FIZZ</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Kalista" if BOARD_GOOGLE_KALISTA</span><br><span> </span><br><span> config MAINBOARD_FAMILY</span><br><span> string</span><br><span> default "Google_Fizz" if BOARD_GOOGLE_FIZZ</span><br><span style="color: hsl(120, 100%, 40%);">+ default "Google_Kalista" if BOARD_GOOGLE_KALISTA</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>@@ -75,9 +81,16 @@</span><br><span> config VARIANT_DIR</span><br><span> string</span><br><span> default "fizz" if BOARD_GOOGLE_FIZZ</span><br><span style="color: hsl(120, 100%, 40%);">+ default "kalista" if BOARD_GOOGLE_KALISTA</span><br><span> </span><br><span> config INCLUDE_NHLT_BLOBS</span><br><span> bool "Include blobs for audio."</span><br><span> select NHLT_RT5663</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config INCLUDE_NHLT_BLOBS_KALISTA</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Include blobs for kalista audio."</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_DA7219</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_DMIC_4CH</span><br><span style="color: hsl(120, 100%, 40%);">+ select NHLT_MAX98357</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # BOARD_GOOGLE_BASEBOARD_FIZZ</span><br><span>diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name</span><br><span>index 28c9700..2911b21 100644</span><br><span>--- a/src/mainboard/google/fizz/Kconfig.name</span><br><span>+++ b/src/mainboard/google/fizz/Kconfig.name</span><br><span>@@ -1,3 +1,7 @@</span><br><span> config BOARD_GOOGLE_FIZZ</span><br><span> bool "Fizz"</span><br><span> select BOARD_GOOGLE_BASEBOARD_FIZZ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_GOOGLE_KALISTA</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Kalista"</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_GOOGLE_BASEBOARD_FIZZ</span><br><span>diff --git a/src/mainboard/google/fizz/variants/kalista/Makefile.inc b/src/mainboard/google/fizz/variants/kalista/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..0ad298b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/kalista/Makefile.inc</span><br><span>@@ -0,0 +1,4 @@</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += nhlt.c</span><br><span>diff --git a/src/mainboard/google/fizz/variants/kalista/devicetree.cb b/src/mainboard/google/fizz/variants/kalista/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..c563b0d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/kalista/devicetree.cb</span><br><span>@@ -0,0 +1,510 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/skylake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Deep Sx states</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_ac" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s3_enable_dc" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_ac" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_dc" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Mapping of USB port # to device</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-----------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Device | Port# | Rev |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-----------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| USB C | 1 | 2/3 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| USB A Rear | 2 | 2/3 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| USB A Front | 3 | 2/3 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| USB A Front | 4 | 2/3 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| USB A Rear | 5 | 2 on base celeron, 2/3 all others |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| USB A Rear | 6 | 2 on base celeron, 2/3 all others |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Bluetooth | 7 | |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Daughter Board | 8 | |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Touchsreen | 10 | |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-----------------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Bitmap for Wake Enable on USB attach/detach</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_WAKE_ENABLE(3) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_WAKE_ENABLE(4) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_WAKE_ENABLE(5) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_WAKE_ENABLE(6)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_WAKE_ENABLE(3) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_WAKE_ENABLE(4) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_WAKE_ENABLE(5) | \</span><br><span style="color: hsl(120, 100%, 40%);">+ USB_PORT_WAKE_ENABLE(6)"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "GPP_E"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c0201"</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC memory map range is 0x900-0x9ff</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x00fc0901"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable S0ix</span><br><span style="color: hsl(120, 100%, 40%);">+ register "s0ix_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ProbelessTrace" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableLan" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableSata" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataMode" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[0]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsDevSlp[1]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPwrOptEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableAzalia" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DspEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IoBufferOwnership" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableTraceHub" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SsicPortEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Cio2Enable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsSdCardEnabled" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PttSwitch" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "InternalGfx" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SkipExtGfxScan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Device4Enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "HeciEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIrqConfigSirqEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS3MinAssert" = "2" # 50ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS4MinAssert" = "1" # 1s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpSusMinAssert" = "1" # 500ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpAMinAssert" = "3" # 2s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmTimerDisabled" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SendVrMbxCmd" = "1" # IMVP8 workaround</span><br><span style="color: hsl(120, 100%, 40%);">+ register "VmxEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intersil VR c-state issue workaround</span><br><span style="color: hsl(120, 100%, 40%);">+ # send VR mailbox command for IA/GT/SA rails</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IslVrCmd" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "PCH_IRQ10"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "PCH_IRQ11"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # VR Settings Configuration for 4 Domains</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Domain/Setting | SA | IA | GTUS | GTS |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi1Threshold | 20A | 20A | 20A | 20A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi2Threshold | 4A | 5A | 5A | 5A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Threshold | 1A | 1A | 1A | 1A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Enable | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi4Enable | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonSlope | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonOffset | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| IccMax | 7A | 34A | 35A | 35A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| AcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| DcLoadline(ohm)| 10.3m | 2.4m | 3.1m | 3.1m |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #Note: IccMax settings are moved to SoC code</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(4),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 1030,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 1030,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_IA_CORE]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 240,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 240,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_UNSLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 310,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 310,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_SLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = VR_CFG_AMP(20),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = VR_CFG_AMP(5),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = VR_CFG_AMP(1),</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 1520,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ac_loadline = 310,</span><br><span style="color: hsl(120, 100%, 40%);">+ .dc_loadline = 310,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 3(x1) for LAN.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 3 uses SRCCLKREQ0#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[2]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 3, Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 3, Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[2]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 3 uses uses CLK SRC 0</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[2]" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 4(x1) for WLAN.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 4 uses SRCCLKREQ5#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[3]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 4, Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 4, Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[3]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 4 uses uses CLK SRC 5</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[3]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 5(x4) for NVMe.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 5 uses SRCCLKREQ1#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 5, Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 5, Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 5 uses CLK SRC 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[4]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 9 for BtoB.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 9 uses SRCCLKREQ2#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[8]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 9, Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 9, Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 9 uses uses CLK SRC 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[8]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 11 for BtoB.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 11 uses SRCCLKREQ2#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[10]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 11, Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 11, Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[10]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 11 uses uses CLK SRC 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[10]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Root port 12 for BtoB.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable CLKREQ#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 12 uses SRCCLKREQ2#</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[11]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 12, Enable Advanced Error Reporting</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpAdvancedErrorReporting[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 12, Enable Latency Tolerance Reporting Mechanism</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpLtrEnable[11]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP 12 uses uses CLK SRC 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[11]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-A Rear</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Front</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Front</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A Rear</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Touchscreen</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Front</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Rear</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # HDMI CEC</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[2]" = "I2C_VOLTAGE_3V3" # Debug</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Intel Common SoC Config</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Field | Value |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| GSPI0 | cr50 TPM. Early init is |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | required to set up a BAR |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | for TPM communication |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| | before memory is up |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| I2C5 | Audio |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+-------------------+---------------------------+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gspi[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_mhz = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ .early_init = 1,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .i2c[5] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed_config[0] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .speed = I2C_SPEED_FAST,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scl_lcnt = 194,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scl_hcnt = 100,</span><br><span style="color: hsl(120, 100%, 40%);">+ .sda_hold = 36,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Must leave UART0 enabled or SD/eMMC will not work as PCI</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoDevMode" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi0] = PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart0] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tdp_psyspl2" = "90"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "psys_pmax" = "120"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tcc_offset" = "6" # TCC of 94C</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Use default SD card detect GPIO configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdcard_cd_gpio_default" = "GPP_A7"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""Root Hub""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_HUB"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 0.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Type-C Rear""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Type-A Rear Left""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.1 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Type-A Front Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Type-A Front Left""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.3 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Type-A Rear Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.4 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Type-A Rear Middle""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.5 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Bluetooth""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.6 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB2 Touchscreen""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_INTERNAL"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 2.9 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-C Rear""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-A Rear Left""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.1 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-A Front Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.2 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-A Front Left""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.3 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-A Rear Right""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.4 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/usb/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "desc" = ""USB3 Type-A Rear Middle""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "type" = "UPC_TYPE_USB3_A"</span><br><span style="color: hsl(120, 100%, 40%);">+ device usb 3.5 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 off end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 on end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 off end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/generic/max98357a</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdmode_delay" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device generic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/da7219</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "btn_cfg" = "50"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mic_det_thr" = "500"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_ins_deb" = "20"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_det_rate" = ""32ms_64ms""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "jack_rem_deb" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "a_d_btn_thr" = "0xa"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "d_b_btn_thr" = "0x16"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "b_c_btn_thr" = "0x21"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c_mic_btn_thr" = "0x3e"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "btn_avg" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "adc_1bit_rpt" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "micbias_lvl" = "2600"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "mic_amp_in_sel" = ""diff""</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 1a on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 off end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCI Express Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCI Express Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/net</span><br><span style="color: hsl(120, 100%, 40%);">+ register "customized_leds" = "0x0fa5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_PCI_EXP"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "device_index" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/intel/wifi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wake" = "GPE0_PCI_EXP"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 4 for WLAN</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on end # PCI Express Port 5 for NVMe</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # PCI Express Port 9 for 2nd LAN</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/net</span><br><span style="color: hsl(120, 100%, 40%);">+ register "customized_leds" = "0x0fa5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "device_index" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCI Express Port 9 for BtoB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 on end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 on end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 off end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/spi/acpi</span><br><span style="color: hsl(120, 100%, 40%);">+ register "hid" = "ACPI_DT_NAMESPACE_HID"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "compat_string" = ""google,cr50""</span><br><span style="color: hsl(120, 100%, 40%);">+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"</span><br><span style="color: hsl(120, 100%, 40%);">+ device spi 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 off end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.4 off end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.5 off end # SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.6 on end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/google/chromeec</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/google/fizz/variants/kalista/gpio.c b/src/mainboard/google/fizz/variants/kalista/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..98231d8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/kalista/gpio.c</span><br><span>@@ -0,0 +1,278 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <commonlib/helpers.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Leave eSPI pins untouched from default settings */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_IO3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_CS# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ EDGE), /* SD_CDZ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* eSPI mode */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI_RESET# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_SPK_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP2 */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* TOUCHSCREEN_RST# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* PCH_TS_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* CLK_PCIE_LAN_REQ# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCIE_CLKREQ_SSD# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCIE_CLKREQ_NGFF1# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCIE_CLKREQ_WLAN# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* VR_DISABLE_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* HWA_TRST_N */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBALERT# */ PAD_CFG_NC(GPP_C2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0CLK */ PAD_CFG_NC(GPP_C3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0DATA */ PAD_CFG_NC(GPP_C4),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* EC_IN_RW */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* GPIO1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* GPIO2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* V3P3_CCD_EN */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* GPIO4 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SKU_ID0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SKU_ID1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SKU_ID2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SKU_ID3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SDA */ PAD_CFG_NC(GPP_C18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SCREW_SPI_WP_STATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCH_I2C0_8625_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCH_I2C0_8625_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLTRST, EDGE), /* HP_IRQ_GPIO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* OEM_ID1 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* OEM_ID2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* OEM_ID3 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* PCH_DMIC_CLK0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* PCH_DMIC_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* BOOT_BEEP_OVERRIDE */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLTRST), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* MB_PCIE_SATA#_DET */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* DB_PCIE_SATA#_DET */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* Rear Dual-Stack USB Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* Front USB Ports */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* Rear Single USB Port */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* INT_HDMI_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* DDI2_HPD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* HDMI_DDCCLK_SW */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* HDMI_DDCCLK_DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLCLK */ PAD_CFG_GPO(GPP_E22, 1, DEEP), /* DP_RST_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* DDPD_CTRLDATA */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* DP_PD_L */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S_2_BCLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S_2_FS_LRC */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_2_TX_DAC */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_I2C2_H1_3V3_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_I2C2_H1_3V3_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_NC(GPP_F8),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SCL */ PAD_CFG_NC(GPP_F9),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_I2C2_AUDIO_1V8_SDA */</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_I2C2_AUDIO_1V8_SCL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),</span><br><span style="color: hsl(120, 100%, 40%);">+/* RSVD */ PAD_CFG_NC(GPP_F23),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */</span><br><span style="color: hsl(120, 100%, 40%);">+/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* RSVD */ PAD_CFG_NC(GPD7),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* LANPHYC */ PAD_CFG_NC(GPD11),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in bootblock */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_CS_L */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_CLK */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_MISO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* PCH_SPI_H1_3V3_MOSI */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ PLTRST), /* H1_PCH_INT_ODL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Ensure UART pins are in native mode for H1. */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,</span><br><span style="color: hsl(120, 100%, 40%);">+ DEEP), /* SCREW_SPI_WP_STATUS */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP,</span><br><span style="color: hsl(120, 100%, 40%);">+ NF1), /* MB_PCIE_SATA#_DET */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pad_config *variant_early_gpio_table(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(early_gpio_table);</span><br><span style="color: hsl(120, 100%, 40%);">+ return early_gpio_table;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct cros_gpio cros_gpios[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct cros_gpio *variant_cros_gpios(size_t *num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *num = ARRAY_SIZE(cros_gpios);</span><br><span style="color: hsl(120, 100%, 40%);">+ return cros_gpios;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/fizz/variants/kalista/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/kalista/include/variant/acpi/dptf.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..a9afa73</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/kalista/include/variant/acpi/dptf.asl</span><br><span>@@ -0,0 +1,16 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/acpi/dptf.asl></span><br><span>diff --git a/src/mainboard/google/fizz/variants/kalista/include/variant/ec.h b/src/mainboard/google/fizz/variants/kalista/include/variant/ec.h</span><br><span>new file mode 100644</span><br><span>index 0000000..3d4fc8f</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/kalista/include/variant/ec.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_EC_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_EC_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_EC_H__ */</span><br><span>diff --git a/src/mainboard/google/fizz/variants/kalista/include/variant/gpio.h b/src/mainboard/google/fizz/variants/kalista/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..cd34cf0</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/kalista/include/variant/gpio.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+#define __MAINBOARD_GPIO_H__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* __MAINBOARD_GPIO_H__ */</span><br><span>diff --git a/src/mainboard/google/fizz/variants/kalista/nhlt.c b/src/mainboard/google/fizz/variants/kalista/nhlt.c</span><br><span>new file mode 100644</span><br><span>index 0000000..af02179</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/google/fizz/variants/kalista/nhlt.c</span><br><span>@@ -0,0 +1,44 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <baseboard/variants.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <nhlt.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nhlt.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_nhlt_init(struct nhlt *nhlt)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* 4 Channel DMIC array. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (nhlt_soc_add_dmic_array(nhlt, 4))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Dialog DA7219 Headset codec. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Couldn't add Dialog DA7219.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MAXIM Smart Amps for left and right speakers. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void variant_nhlt_oem_overrides(const char **oem_id,</span><br><span style="color: hsl(120, 100%, 40%);">+ const char **oem_table_id,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t *oem_revision)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ *oem_id = "GOOGLE";</span><br><span style="color: hsl(120, 100%, 40%);">+ *oem_table_id = "KALISTA";</span><br><span style="color: hsl(120, 100%, 40%);">+ *oem_revision = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29205">change 29205</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29205"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I808c5e0883049575cbedd181c249a78a833fa96a </div>
<div style="display:none"> Gerrit-Change-Number: 29205 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: David Wu <david_wu@quanta.corp-partner.google.com> </div>