[coreboot-gerrit] Change in coreboot[master]: Typo fix (cosmetic)
Peter Lemenkov (Code Review)
gerrit at coreboot.org
Fri Oct 19 16:59:19 CEST 2018
Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29196
Change subject: Typo fix (cosmetic)
......................................................................
Typo fix (cosmetic)
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b
Signed-off-by: Peter Lemenkov <lemenkov at gmail.com>
---
M src/northbridge/amd/amdht/h3finit.c
M src/southbridge/amd/sb800/hda.c
M src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
M src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
9 files changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29196/1
diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index fc0c2d2..1e2d1a0 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -1601,7 +1601,7 @@
{
if (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) /* Must be a CPU link */
continue;
- if (pDat->PortList[i].Link < 4) /* Only look for for sublink1's */
+ if (pDat->PortList[i].Link < 4) /* Only look for sublink1's */
continue;
for (j = 0; j < pDat->TotalLinks*2; j++)
diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c
index 78e9862..feb0eb2 100644
--- a/src/southbridge/amd/sb800/hda.c
+++ b/src/southbridge/amd/sb800/hda.c
@@ -89,7 +89,7 @@
}
/**
- * Wait 50usec for for the codec to indicate it is ready
+ * Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
static int wait_for_ready(void *base)
@@ -110,7 +110,7 @@
}
/**
- * Wait 50usec for for the codec to indicate that it accepted
+ * Wait 50usec for the codec to indicate that it accepted
* the previous command. No response would imply that the code
* is non-operative
*/
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
index ba4d4e7..2f4e098 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c
@@ -115,7 +115,7 @@
/*---------------------------------------------------------------------------------------*/
/**
- * BSC entry point for for enabling Core Performance Boost.
+ * BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
index c7efe43..6d28bfe 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c
@@ -113,7 +113,7 @@
/*---------------------------------------------------------------------------------------*/
/**
- * BSC entry point for for enabling Core Performance Boost.
+ * BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
index 77f0b65..1660c49 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
@@ -85,7 +85,7 @@
/*---------------------------------------------------------------------------------------*/
/**
- * BSC entry point for for adding MMIO map
+ * BSC entry point for adding MMIO map
*
* program MMIO base/limit registers
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
index db00c58..8d2fa34 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
@@ -141,7 +141,7 @@
/*---------------------------------------------------------------------------------------*/
/**
- * BSC entry point for for enabling Core Performance Boost.
+ * BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
index cf1d0d8..714f970 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
@@ -85,7 +85,7 @@
/*---------------------------------------------------------------------------------------*/
/**
- * BSC entry point for for adding MMIO map
+ * BSC entry point for adding MMIO map
*
* program MMIO base/limit registers
*
diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
index 192a8a9..0fcc180 100644
--- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
+++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
@@ -3295,7 +3295,7 @@
mem_size_mbytes *= 2;
}
- /* Mask with 1 bits set for for each active rank, allowing 2 bits per dimm.
+ /* Mask with 1 bits set for each active rank, allowing 2 bits per dimm.
** This makes later calculations simpler, as a variety of CSRs use this layout.
** This init needs to be updated for dual configs (ie non-identical DIMMs).
** Bit 0 = dimm0, rank 0
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
index 12c6e44..d03a844 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
@@ -2978,8 +2978,8 @@
**/
UINT8 ThreeStrikeCounterDisable;
-/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
- Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
+/** Offset 0x0899 - Set HW P-State Interrupts Enabled for MISC_PWR_MGMT
+ Set HW P-State Interrupts Enabled for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 HwpInterruptControl;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b
Gerrit-Change-Number: 29196
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Lemenkov <lemenkov at gmail.com>
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