<p>Peter Lemenkov has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29196">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Typo fix (cosmetic)<br><br>Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b<br>Signed-off-by: Peter Lemenkov <lemenkov@gmail.com><br>---<br>M src/northbridge/amd/amdht/h3finit.c<br>M src/southbridge/amd/sb800/hda.c<br>M src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c<br>M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c<br>M src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c<br>M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c<br>M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c<br>M src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c<br>M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h<br>9 files changed, 11 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/29196/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c</span><br><span>index fc0c2d2..1e2d1a0 100644</span><br><span>--- a/src/northbridge/amd/amdht/h3finit.c</span><br><span>+++ b/src/northbridge/amd/amdht/h3finit.c</span><br><span>@@ -1601,7 +1601,7 @@</span><br><span> {</span><br><span> if (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) /* Must be a CPU link */</span><br><span> continue;</span><br><span style="color: hsl(0, 100%, 40%);">- if (pDat->PortList[i].Link < 4) /* Only look for for sublink1's */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (pDat->PortList[i].Link < 4) /* Only look for sublink1's */</span><br><span> continue;</span><br><span> </span><br><span> for (j = 0; j < pDat->TotalLinks*2; j++)</span><br><span>diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c</span><br><span>index 78e9862..feb0eb2 100644</span><br><span>--- a/src/southbridge/amd/sb800/hda.c</span><br><span>+++ b/src/southbridge/amd/sb800/hda.c</span><br><span>@@ -89,7 +89,7 @@</span><br><span> }</span><br><span> </span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * Wait 50usec for for the codec to indicate it is ready</span><br><span style="color: hsl(120, 100%, 40%);">+ * Wait 50usec for the codec to indicate it is ready</span><br><span> * no response would imply that the codec is non-operative</span><br><span> */</span><br><span> static int wait_for_ready(void *base)</span><br><span>@@ -110,7 +110,7 @@</span><br><span> }</span><br><span> </span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * Wait 50usec for for the codec to indicate that it accepted</span><br><span style="color: hsl(120, 100%, 40%);">+ * Wait 50usec for the codec to indicate that it accepted</span><br><span> * the previous command. No response would imply that the code</span><br><span> * is non-operative</span><br><span> */</span><br><span>diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c</span><br><span>index ba4d4e7..2f4e098 100644</span><br><span>--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c</span><br><span>+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c</span><br><span>@@ -115,7 +115,7 @@</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * BSC entry point for for enabling Core Performance Boost.</span><br><span style="color: hsl(120, 100%, 40%);">+ * BSC entry point for enabling Core Performance Boost.</span><br><span> *</span><br><span> * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.</span><br><span> *</span><br><span>diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c</span><br><span>index c7efe43..6d28bfe 100644</span><br><span>--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c</span><br><span>+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c</span><br><span>@@ -113,7 +113,7 @@</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * BSC entry point for for enabling Core Performance Boost.</span><br><span style="color: hsl(120, 100%, 40%);">+ * BSC entry point for enabling Core Performance Boost.</span><br><span> *</span><br><span> * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.</span><br><span> *</span><br><span>diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c</span><br><span>index 77f0b65..1660c49 100644</span><br><span>--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c</span><br><span>+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c</span><br><span>@@ -85,7 +85,7 @@</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * BSC entry point for for adding MMIO map</span><br><span style="color: hsl(120, 100%, 40%);">+ * BSC entry point for adding MMIO map</span><br><span> *</span><br><span> * program MMIO base/limit registers</span><br><span> *</span><br><span>diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c</span><br><span>index db00c58..8d2fa34 100644</span><br><span>--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c</span><br><span>+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c</span><br><span>@@ -141,7 +141,7 @@</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * BSC entry point for for enabling Core Performance Boost.</span><br><span style="color: hsl(120, 100%, 40%);">+ * BSC entry point for enabling Core Performance Boost.</span><br><span> *</span><br><span> * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.</span><br><span> *</span><br><span>diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c</span><br><span>index cf1d0d8..714f970 100644</span><br><span>--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c</span><br><span>+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c</span><br><span>@@ -85,7 +85,7 @@</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span style="color: hsl(0, 100%, 40%);">- * BSC entry point for for adding MMIO map</span><br><span style="color: hsl(120, 100%, 40%);">+ * BSC entry point for adding MMIO map</span><br><span> *</span><br><span> * program MMIO base/limit registers</span><br><span> *</span><br><span>diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c</span><br><span>index 192a8a9..0fcc180 100644</span><br><span>--- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c</span><br><span>+++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c</span><br><span>@@ -3295,7 +3295,7 @@</span><br><span> mem_size_mbytes *= 2;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Mask with 1 bits set for for each active rank, allowing 2 bits per dimm.</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Mask with 1 bits set for each active rank, allowing 2 bits per dimm.</span><br><span> ** This makes later calculations simpler, as a variety of CSRs use this layout.</span><br><span> ** This init needs to be updated for dual configs (ie non-identical DIMMs).</span><br><span> ** Bit 0 = dimm0, rank 0</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>index 12c6e44..d03a844 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h</span><br><span>@@ -2978,8 +2978,8 @@</span><br><span> **/</span><br><span> UINT8 ThreeStrikeCounterDisable;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT</span><br><span style="color: hsl(0, 100%, 40%);">- Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0899 - Set HW P-State Interrupts Enabled for MISC_PWR_MGMT</span><br><span style="color: hsl(120, 100%, 40%);">+ Set HW P-State Interrupts Enabled for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 HwpInterruptControl;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29196">change 29196</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29196"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b </div>
<div style="display:none"> Gerrit-Change-Number: 29196 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Peter Lemenkov <lemenkov@gmail.com> </div>