[coreboot-gerrit] Change in coreboot[master]: Use standard pci_dev_set_subsystem function where possible
Peter Lemenkov (Code Review)
gerrit at coreboot.org
Fri Oct 19 16:24:38 CEST 2018
Peter Lemenkov has uploaded a new patch set (#2). ( https://review.coreboot.org/29195 )
Change subject: Use standard pci_dev_set_subsystem function where possible
......................................................................
Use standard pci_dev_set_subsystem function where possible
We use the following pattern in many places:
static void subsystemname_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
Surprisingly but since commit fd891291 with Change-Id
I5027331a6adf9109767415ba22dfcb17b35ef54b ("pci_device: Write vendor ID
to subsystem vendor ID") pci_dev_enable_resources function does these
checks and fills dev struct fields with vendor and device. So neither
vendor nor device cannot be NULL.
Let's use this generic function and avoid code duplication.
We can replace set_subsystem function entirely in case of a standard
address PCI_SUBSYSTEM_VENDOR_ID (0x2C), or at least simplify it (see
src/drivers/ricoh/rce822/rce822.c for example).
I've skipped three files:
* src/southbridge/intel/i82801gx/pci.c
* src/southbridge/intel/bd82x6x/pci.c
* src/southbridge/intel/lynxpoint/pci.c
These three files have calls to the set_subsystem function inside their
own code, and I am not yet familiar with the codebase well enough to say
for certain if it's fine or no to remove these checks for NULL.
Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104
Signed-off-by: Peter Lemenkov <lemenkov at gmail.com>
---
M src/drivers/ricoh/rce822/rce822.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/fsp_rangeley/northbridge.c
M src/northbridge/intel/fsp_sandybridge/gma.c
M src/northbridge/intel/fsp_sandybridge/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/intel/baytrail/chip.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/braswell/chip.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/broadwell/chip.c
M src/soc/intel/broadwell/ehci.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/fsp_baytrail/chip.c
M src/soc/intel/fsp_broadwell_de/chip.c
M src/southbridge/amd/amd8111/ac97.c
M src/southbridge/broadcom/bcm5785/sb_pci_main.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/fsp_bd82x6x/azalia.c
M src/southbridge/intel/fsp_bd82x6x/lpc.c
M src/southbridge/intel/fsp_bd82x6x/me.c
M src/southbridge/intel/fsp_bd82x6x/me_8.x.c
M src/southbridge/intel/fsp_bd82x6x/sata.c
M src/southbridge/intel/fsp_i89xx/lpc.c
M src/southbridge/intel/fsp_i89xx/me.c
M src/southbridge/intel/fsp_i89xx/me_8.x.c
M src/southbridge/intel/fsp_i89xx/sata.c
M src/southbridge/intel/fsp_rangeley/lpc.c
M src/southbridge/intel/fsp_rangeley/sata.c
M src/southbridge/intel/fsp_rangeley/smbus.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/hdaudio.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/hdaudio.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/nvidia/mcp55/azalia.c
94 files changed, 118 insertions(+), 1,080 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29195/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104
Gerrit-Change-Number: 29195
Gerrit-PatchSet: 2
Gerrit-Owner: Peter Lemenkov <lemenkov at gmail.com>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
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