<p>Peter Lemenkov <strong>uploaded patch set #2</strong> to this change.</p><p><a href="https://review.coreboot.org/29195">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Use standard pci_dev_set_subsystem function where possible<br><br>We use the following pattern in many places:<br><br>static void subsystemname_set_subsystem(struct device *dev, unsigned int vendor,<br> unsigned int device)<br>{<br> if (!vendor || !device) {<br> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br> pci_read_config32(dev, PCI_VENDOR_ID));<br> } else {<br> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br> ((device & 0xffff) << 16) | (vendor & 0xffff));<br> }<br>}<br><br>Surprisingly but since commit fd891291 with Change-Id<br>I5027331a6adf9109767415ba22dfcb17b35ef54b ("pci_device: Write vendor ID<br>to subsystem vendor ID") pci_dev_enable_resources function does these<br>checks and fills dev struct fields with vendor and device. So neither<br>vendor nor device cannot be NULL.<br><br>Let's use this generic function and avoid code duplication.<br><br>We can replace set_subsystem function entirely in case of a standard<br>address PCI_SUBSYSTEM_VENDOR_ID (0x2C), or at least simplify it (see<br>src/drivers/ricoh/rce822/rce822.c for example).<br><br>I've skipped three files:<br><br>* src/southbridge/intel/i82801gx/pci.c<br>* src/southbridge/intel/bd82x6x/pci.c<br>* src/southbridge/intel/lynxpoint/pci.c<br><br>These three files have calls to the set_subsystem function inside their<br>own code, and I am not yet familiar with the codebase well enough to say<br>for certain if it's fine or no to remove these checks for NULL.<br><br>Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104<br>Signed-off-by: Peter Lemenkov <lemenkov@gmail.com><br>---<br>M src/drivers/ricoh/rce822/rce822.c<br>M src/northbridge/intel/e7505/northbridge.c<br>M src/northbridge/intel/fsp_rangeley/northbridge.c<br>M src/northbridge/intel/fsp_sandybridge/gma.c<br>M src/northbridge/intel/fsp_sandybridge/northbridge.c<br>M src/northbridge/intel/gm45/gma.c<br>M src/northbridge/intel/haswell/gma.c<br>M src/northbridge/intel/haswell/minihd.c<br>M src/northbridge/intel/haswell/northbridge.c<br>M src/northbridge/intel/i945/gma.c<br>M src/northbridge/intel/i945/northbridge.c<br>M src/northbridge/intel/nehalem/gma.c<br>M src/northbridge/intel/nehalem/northbridge.c<br>M src/northbridge/intel/pineview/gma.c<br>M src/northbridge/intel/sandybridge/gma.c<br>M src/northbridge/intel/sandybridge/northbridge.c<br>M src/northbridge/intel/sandybridge/pcie.c<br>M src/northbridge/intel/x4x/gma.c<br>M src/soc/intel/baytrail/chip.c<br>M src/soc/intel/baytrail/pcie.c<br>M src/soc/intel/braswell/chip.c<br>M src/soc/intel/braswell/pcie.c<br>M src/soc/intel/broadwell/chip.c<br>M src/soc/intel/broadwell/ehci.c<br>M src/soc/intel/broadwell/pcie.c<br>M src/soc/intel/common/block/pcie/pcie.c<br>M src/soc/intel/denverton_ns/chip.c<br>M src/soc/intel/fsp_baytrail/chip.c<br>M src/soc/intel/fsp_broadwell_de/chip.c<br>M src/southbridge/amd/amd8111/ac97.c<br>M src/southbridge/broadcom/bcm5785/sb_pci_main.c<br>M src/southbridge/intel/bd82x6x/azalia.c<br>M src/southbridge/intel/bd82x6x/lpc.c<br>M src/southbridge/intel/bd82x6x/me.c<br>M src/southbridge/intel/bd82x6x/me_8.x.c<br>M src/southbridge/intel/bd82x6x/pcie.c<br>M src/southbridge/intel/bd82x6x/sata.c<br>M src/southbridge/intel/bd82x6x/smbus.c<br>M src/southbridge/intel/bd82x6x/usb_ehci.c<br>M src/southbridge/intel/bd82x6x/usb_xhci.c<br>M src/southbridge/intel/fsp_bd82x6x/azalia.c<br>M src/southbridge/intel/fsp_bd82x6x/lpc.c<br>M src/southbridge/intel/fsp_bd82x6x/me.c<br>M src/southbridge/intel/fsp_bd82x6x/me_8.x.c<br>M src/southbridge/intel/fsp_bd82x6x/sata.c<br>M src/southbridge/intel/fsp_i89xx/lpc.c<br>M src/southbridge/intel/fsp_i89xx/me.c<br>M src/southbridge/intel/fsp_i89xx/me_8.x.c<br>M src/southbridge/intel/fsp_i89xx/sata.c<br>M src/southbridge/intel/fsp_rangeley/lpc.c<br>M src/southbridge/intel/fsp_rangeley/sata.c<br>M src/southbridge/intel/fsp_rangeley/smbus.c<br>M src/southbridge/intel/i82801gx/ac97.c<br>M src/southbridge/intel/i82801gx/azalia.c<br>M src/southbridge/intel/i82801gx/ide.c<br>M src/southbridge/intel/i82801gx/lpc.c<br>M src/southbridge/intel/i82801gx/pcie.c<br>M src/southbridge/intel/i82801gx/sata.c<br>M src/southbridge/intel/i82801gx/smbus.c<br>M src/southbridge/intel/i82801gx/usb.c<br>M src/southbridge/intel/i82801gx/usb_ehci.c<br>M src/southbridge/intel/i82801ix/hdaudio.c<br>M src/southbridge/intel/i82801ix/lpc.c<br>M src/southbridge/intel/i82801ix/pci.c<br>M src/southbridge/intel/i82801ix/pcie.c<br>M src/southbridge/intel/i82801ix/sata.c<br>M src/southbridge/intel/i82801ix/smbus.c<br>M src/southbridge/intel/i82801ix/thermal.c<br>M src/southbridge/intel/i82801ix/usb_ehci.c<br>M src/southbridge/intel/i82801jx/hdaudio.c<br>M src/southbridge/intel/i82801jx/lpc.c<br>M src/southbridge/intel/i82801jx/pci.c<br>M src/southbridge/intel/i82801jx/pcie.c<br>M src/southbridge/intel/i82801jx/sata.c<br>M src/southbridge/intel/i82801jx/smbus.c<br>M src/southbridge/intel/i82801jx/thermal.c<br>M src/southbridge/intel/i82801jx/usb_ehci.c<br>M src/southbridge/intel/ibexpeak/azalia.c<br>M src/southbridge/intel/ibexpeak/lpc.c<br>M src/southbridge/intel/ibexpeak/me.c<br>M src/southbridge/intel/ibexpeak/sata.c<br>M src/southbridge/intel/ibexpeak/smbus.c<br>M src/southbridge/intel/ibexpeak/thermal.c<br>M src/southbridge/intel/ibexpeak/usb_ehci.c<br>M src/southbridge/intel/lynxpoint/azalia.c<br>M src/southbridge/intel/lynxpoint/lpc.c<br>M src/southbridge/intel/lynxpoint/me_9.x.c<br>M src/southbridge/intel/lynxpoint/pcie.c<br>M src/southbridge/intel/lynxpoint/sata.c<br>M src/southbridge/intel/lynxpoint/serialio.c<br>M src/southbridge/intel/lynxpoint/smbus.c<br>M src/southbridge/intel/lynxpoint/usb_ehci.c<br>M src/southbridge/intel/lynxpoint/usb_xhci.c<br>M src/southbridge/nvidia/mcp55/azalia.c<br>94 files changed, 118 insertions(+), 1,080 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/29195/2</pre><p>To view, visit <a href="https://review.coreboot.org/29195">change 29195</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29195"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newpatchset </div>
<div style="display:none"> Gerrit-Change-Id: I90c1ee9ddf8341291ccb82c1f699410c6e9fc104 </div>
<div style="display:none"> Gerrit-Change-Number: 29195 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Peter Lemenkov <lemenkov@gmail.com> </div>
<div style="display:none"> Gerrit-CC: build bot (Jenkins) <no-reply@coreboot.org> </div>