[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge/include/soc: Fix NB IOAPIC definitions

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29155


Change subject: amd/stoneyridge/include/soc: Fix NB IOAPIC definitions
......................................................................

amd/stoneyridge/include/soc: Fix NB IOAPIC definitions

There's no indication that they are accessed through D0F0. Add a D0F0 header
and move IOAPIC definitions under it. The registers defined to be accessed
through index/data pair should be indented relative to the index/data pair
definition.

BUG=b:117754786
TEST=Build grunt.

Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/northbridge.h
1 file changed, 22 insertions(+), 20 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29155/1

diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 56ae363..7f7ac5d 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -20,6 +20,28 @@
 #include <arch/io.h>
 #include <device/device.h>
 
+/* D0F0 - Root Complex */
+
+/* NB IOAPIC registers */
+#define NB_IOAPIC_INDEX		0xf8
+#define NB_IOAPIC_DATA		0xfc
+#define  NB_IOAPIC_FEATURE_CTRL	0x00
+#define  NB_IOAPIC_ADDRESS_LOW	0x01
+#define  NB_IOAPIC_ADDRESS_HIGH	0x02
+#define  NB_IOAPIC_GBIF_IRR	0x0f
+#define  NB_IOAPIC_BR0_IRR	0x10
+#define  NB_IOAPIC_BR1_IRR	0x11
+#define  NB_IOAPIC_BR2_IRR	0x12
+#define  NB_IOAPIC_BR3_IRR	0x13
+#define  NB_IOAPIC_BR4_IRR	0x14
+#define  NB_IOAPIC_APG_IRR	0x2f
+#define  NB_IOAPIC_SPG_IRR	0x30
+#define  NB_IOAPIC_SER_IRQ_IRR	0x31
+#define  NB_IOAPIC_SCRATCH0	0x3e
+#define  NB_IOAPIC_SCRATCH1	0x3f
+
+#define AP_SCRATCH_REG		NB_IOAPIC_SCRATCH0
+
 /* D1F1 - HDA Configuration Registers */
 #define HDA_DEV_CTRL_STATUS	0x60
 #define   HDA_NO_SNOOP_EN	BIT(11)
@@ -32,26 +54,6 @@
 # define HTIC_BIOSR_DETECT	((1 << 5) | (1 << 9) | (1 << 10))
 # define HTIC_COLD_RST_DET	BIT(4)
 
-/* NB IOAPIC registers */
-#define NB_IOAPIC_INDEX		0xf8
-#define NB_IOAPIC_DATA		0xfc
-#define NB_IOAPIC_FEATURE_CTRL	0x00
-#define NB_IOAPIC_ADDRESS_LOW	0x01
-#define NB_IOAPIC_ADDRESS_HIGH	0x02
-#define NB_IOAPIC_GBIF_IRR	0x0f
-#define NB_IOAPIC_BR0_IRR	0x10
-#define NB_IOAPIC_BR1_IRR	0x11
-#define NB_IOAPIC_BR2_IRR	0x12
-#define NB_IOAPIC_BR3_IRR	0x13
-#define NB_IOAPIC_BR4_IRR	0x14
-#define NB_IOAPIC_APG_IRR	0x2f
-#define NB_IOAPIC_SPG_IRR	0x30
-#define NB_IOAPIC_SER_IRQ_IRR	0x31
-#define NB_IOAPIC_SCRATCH0	0x3e
-#define NB_IOAPIC_SCRATCH1	0x3f
-
-#define AP_SCRATCH_REG		NB_IOAPIC_SCRATCH0
-
 /* D18F1 - Address Map Registers */
 
 /* MMIO base and limit */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3
Gerrit-Change-Number: 29155
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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