<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29155">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge/include/soc: Fix NB IOAPIC definitions<br><br>There's no indication that they are accessed through D0F0. Add a D0F0 header<br>and move IOAPIC definitions under it. The registers defined to be accessed<br>through index/data pair should be indented relative to the index/data pair<br>definition.<br><br>BUG=b:117754786<br>TEST=Build grunt.<br><br>Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>1 file changed, 22 insertions(+), 20 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29155/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>index 56ae363..7f7ac5d 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h</span><br><span>@@ -20,6 +20,28 @@</span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* D0F0 - Root Complex */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* NB IOAPIC registers */</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_INDEX 0xf8</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_DATA 0xfc</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_FEATURE_CTRL 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_ADDRESS_LOW 0x01</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_ADDRESS_HIGH 0x02</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_GBIF_IRR 0x0f</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR0_IRR 0x10</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR1_IRR 0x11</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR2_IRR 0x12</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR3_IRR 0x13</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_BR4_IRR 0x14</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_APG_IRR 0x2f</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_SPG_IRR 0x30</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_SER_IRQ_IRR 0x31</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_SCRATCH0 0x3e</span><br><span style="color: hsl(120, 100%, 40%);">+#define NB_IOAPIC_SCRATCH1 0x3f</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* D1F1 - HDA Configuration Registers */</span><br><span> #define HDA_DEV_CTRL_STATUS 0x60</span><br><span> #define HDA_NO_SNOOP_EN BIT(11)</span><br><span>@@ -32,26 +54,6 @@</span><br><span> # define HTIC_BIOSR_DETECT ((1 << 5) | (1 << 9) | (1 << 10))</span><br><span> # define HTIC_COLD_RST_DET BIT(4)</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* NB IOAPIC registers */</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_INDEX 0xf8</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_DATA 0xfc</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_FEATURE_CTRL 0x00</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_ADDRESS_LOW 0x01</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_ADDRESS_HIGH 0x02</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_GBIF_IRR 0x0f</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_BR0_IRR 0x10</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_BR1_IRR 0x11</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_BR2_IRR 0x12</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_BR3_IRR 0x13</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_BR4_IRR 0x14</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_APG_IRR 0x2f</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_SPG_IRR 0x30</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_SER_IRQ_IRR 0x31</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_SCRATCH0 0x3e</span><br><span style="color: hsl(0, 100%, 40%);">-#define NB_IOAPIC_SCRATCH1 0x3f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define AP_SCRATCH_REG NB_IOAPIC_SCRATCH0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* D18F1 - Address Map Registers */</span><br><span> </span><br><span> /* MMIO base and limit */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29155">change 29155</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29155"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3 </div>
<div style="display:none"> Gerrit-Change-Number: 29155 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>