[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Prevent disabling of TCO

[Naresh Solanki (Code Review)]

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/29108


Change subject: soc/intel/skylake: Prevent disabling of TCO
......................................................................

soc/intel/skylake: Prevent disabling of TCO

If ACPI PM timer is disabled, TCO also gets disabled.

FSP default config for EnableTcoTimer is disabled, this caused ACPI PM
timer & TCO to be disabled by FSP even when config PmTimerDisable = 0.

Thus update FSPS UPD EnableTcoTimer in accordance to devicetree config
PmTimerDisable.

BUG=None
TEST= Build for Soraka with PmTimerDisable=0 & check if TCO caused
reboot after running shell command: cat >> /dev/watchdog0

Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
M src/soc/intel/skylake/chip_fsp20.c
1 file changed, 1 insertion(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29108/1

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index a2a430e..7cc6de5 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -369,6 +369,7 @@
 	params->SataMode = config->SataMode;
 	params->SataSpeedLimit = config->SataSpeedLimit;
 	params->SataPwrOptEnable = config->SataPwrOptEnable;
+	params->EnableTcoTimer = !config->PmTimerDisabled;
 
 	tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
 	tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd
Gerrit-Change-Number: 29108
Gerrit-PatchSet: 1
Gerrit-Owner: Naresh Solanki <naresh.solanki at intel.com>
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