[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Fix SPI_CMD_TRIGGER coding style

[Martin Roth (Code Review)]

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/29010 )

Change subject: amd/stoneyridge: Fix SPI_CMD_TRIGGER coding style
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amd/stoneyridge: Fix SPI_CMD_TRIGGER coding style

Make the whitespace match surrounding lines and remove unnecessary
parentheses.

Change-Id: I2ed02494ba69237c38af61317e435d9575cefe1c
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Reviewed-on: https://review.coreboot.org/29010
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Richard Spiegel: Looks good to me, approved



diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index c50733b..d4af8a1 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -229,8 +229,8 @@
 #define   EXEC_OPCODE			BIT(16)
 #define SPI_CNTRL1			0x0c
 #define SPI_CMD_CODE			0x45
-#define SPI_CMD_TRIGGER		0x47
-#define   SPI_CMD_TRIGGER_EXECUTE	(BIT(7))
+#define SPI_CMD_TRIGGER			0x47
+#define   SPI_CMD_TRIGGER_EXECUTE	BIT(7)
 #define SPI_TX_BYTE_COUNT		0x48
 #define SPI_RX_BYTE_COUNT		0x4b
 #define SPI_STATUS			0x4c

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I2ed02494ba69237c38af61317e435d9575cefe1c
Gerrit-Change-Number: 29010
Gerrit-PatchSet: 2
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Richard Spiegel <richard.spiegel at silverbackltd.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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