[coreboot-gerrit] Change in coreboot[master]: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic
Joel Kitching (Code Review)
gerrit at coreboot.org
Fri Oct 12 09:29:37 CEST 2018
Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/29060
Change subject: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic
......................................................................
vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic
- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag
- implement vboot_platform_is_resuming on platforms missing it
[ originally https://review.coreboot.org/c/coreboot/+/28750 ]
BUG=b:114018226
TEST=compile coreboot
Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9
Signed-off-by: Joel Kitching <kitching at google.com>
---
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/slippy/chromeos.c
M src/mainboard/google/stout/chromeos.c
M src/mainboard/intel/baskingridge/chromeos.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/stumpy/chromeos.c
M src/security/vboot/vboot_logic.c
M src/soc/intel/baytrail/pmutil.c
M src/soc/intel/braswell/pmutil.c
M src/soc/intel/broadwell/pmutil.c
13 files changed, 120 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29060/1
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c
index ad4eab9..ab89fcf 100644
--- a/src/mainboard/google/beltino/chromeos.c
+++ b/src/mainboard/google/beltino/chromeos.c
@@ -14,10 +14,12 @@
*/
#include <string.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <bootmode.h>
#include <device/device.h>
#include <device/pci.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -98,3 +100,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index 7a74ed5..6836286 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -16,9 +16,11 @@
#include <console/console.h>
#include <string.h>
#include <bootmode.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
@@ -123,3 +125,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
index 335f1f7..e50e1db 100644
--- a/src/mainboard/google/link/chromeos.c
+++ b/src/mainboard/google/link/chromeos.c
@@ -15,6 +15,8 @@
#include <string.h>
#include <bootmode.h>
+#include <arch/acpi.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -76,3 +78,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index b82efba..1bbfcb3 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -13,12 +13,14 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <console/console.h>
#include <string.h>
#include <bootmode.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
@@ -112,3 +114,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c
index e26c3fb..f0e72eb 100644
--- a/src/mainboard/google/slippy/chromeos.c
+++ b/src/mainboard/google/slippy/chromeos.c
@@ -13,8 +13,10 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <string.h>
#include <bootmode.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -49,3 +51,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index 6d77a2a..9981e0a 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -15,10 +15,12 @@
#include <string.h>
#include <bootmode.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
@@ -133,3 +135,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 2f8e27b..d8ef54f 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -15,9 +15,11 @@
#include <string.h>
#include <bootmode.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -98,3 +100,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index 0f672b6..5c55ed3 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -15,10 +15,12 @@
#include <string.h>
#include <bootmode.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -150,3 +152,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 9c34995..5c5383f 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -15,9 +15,11 @@
#include <string.h>
#include <bootmode.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
+#include <security/vboot/vboot_common.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -147,3 +149,11 @@
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c
index dd74722..6e080a3 100644
--- a/src/security/vboot/vboot_logic.c
+++ b/src/security/vboot/vboot_logic.c
@@ -310,7 +310,6 @@
* does verification of memory init and thus must ensure it resumes with
* the same slot that it booted from. */
if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&
- IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) &&
vboot_platform_is_resuming())
ctx.flags |= VB2_CONTEXT_S3_RESUME;
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 30e6d1d..dab5be3 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -14,6 +14,7 @@
*/
#include <stdint.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <cbmem.h>
#include <console/console.h>
@@ -23,6 +24,7 @@
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <security/vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
#if defined(__SIMPLE_DEVICE__)
@@ -384,3 +386,11 @@
{
return rtc_failure();
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 00284d1..85384a61 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <arch/io.h>
#include <cbmem.h>
#include <console/console.h>
@@ -24,6 +25,7 @@
#include <soc/pm.h>
#include <stdint.h>
#include <security/vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
#if defined(__SIMPLE_DEVICE__)
@@ -380,3 +382,11 @@
{
return rtc_failure();
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
+}
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index 3899130..e19025b 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -18,6 +18,7 @@
* and the differences between PCH variants.
*/
+#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
@@ -29,6 +30,7 @@
#include <soc/pm.h>
#include <soc/gpio.h>
#include <security/vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
/* Print status bits with descriptive names */
static void print_status_bits(u32 status, const char *bit_names[])
@@ -473,3 +475,11 @@
{
return rtc_failure();
}
+
+int vboot_platform_is_resuming(void)
+{
+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))
+ return 0;
+
+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9
Gerrit-Change-Number: 29060
Gerrit-PatchSet: 1
Gerrit-Owner: Joel Kitching <kitching at google.com>
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