<p>Joel Kitching has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29060">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic<br><br>- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag<br>- implement vboot_platform_is_resuming on platforms missing it<br><br>[ originally https://review.coreboot.org/c/coreboot/+/28750 ]<br><br>BUG=b:114018226<br>TEST=compile coreboot<br><br>Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9<br>Signed-off-by: Joel Kitching <kitching@google.com><br>---<br>M src/mainboard/google/beltino/chromeos.c<br>M src/mainboard/google/butterfly/chromeos.c<br>M src/mainboard/google/link/chromeos.c<br>M src/mainboard/google/parrot/chromeos.c<br>M src/mainboard/google/slippy/chromeos.c<br>M src/mainboard/google/stout/chromeos.c<br>M src/mainboard/intel/baskingridge/chromeos.c<br>M src/mainboard/samsung/lumpy/chromeos.c<br>M src/mainboard/samsung/stumpy/chromeos.c<br>M src/security/vboot/vboot_logic.c<br>M src/soc/intel/baytrail/pmutil.c<br>M src/soc/intel/braswell/pmutil.c<br>M src/soc/intel/broadwell/pmutil.c<br>13 files changed, 120 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/29060/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c</span><br><span>index ad4eab9..ab89fcf 100644</span><br><span>--- a/src/mainboard/google/beltino/chromeos.c</span><br><span>+++ b/src/mainboard/google/beltino/chromeos.c</span><br><span>@@ -14,10 +14,12 @@</span><br><span> */</span><br><span> </span><br><span> #include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <bootmode.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> #include <southbridge/intel/lynxpoint/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>@@ -98,3 +100,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c</span><br><span>index 7a74ed5..6836286 100644</span><br><span>--- a/src/mainboard/google/butterfly/chromeos.c</span><br><span>+++ b/src/mainboard/google/butterfly/chromeos.c</span><br><span>@@ -16,9 +16,11 @@</span><br><span> #include <console/console.h></span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span>@@ -123,3 +125,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c</span><br><span>index 335f1f7..e50e1db 100644</span><br><span>--- a/src/mainboard/google/link/chromeos.c</span><br><span>+++ b/src/mainboard/google/link/chromeos.c</span><br><span>@@ -15,6 +15,8 @@</span><br><span> </span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>@@ -76,3 +78,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c</span><br><span>index b82efba..1bbfcb3 100644</span><br><span>--- a/src/mainboard/google/parrot/chromeos.c</span><br><span>+++ b/src/mainboard/google/parrot/chromeos.c</span><br><span>@@ -13,12 +13,14 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <console/console.h></span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span>@@ -112,3 +114,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c</span><br><span>index e26c3fb..f0e72eb 100644</span><br><span>--- a/src/mainboard/google/slippy/chromeos.c</span><br><span>+++ b/src/mainboard/google/slippy/chromeos.c</span><br><span>@@ -13,8 +13,10 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> #include <southbridge/intel/lynxpoint/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>@@ -49,3 +51,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c</span><br><span>index 6d77a2a..9981e0a 100644</span><br><span>--- a/src/mainboard/google/stout/chromeos.c</span><br><span>+++ b/src/mainboard/google/stout/chromeos.c</span><br><span>@@ -15,10 +15,12 @@</span><br><span> </span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span>@@ -133,3 +135,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c</span><br><span>index 2f8e27b..d8ef54f 100644</span><br><span>--- a/src/mainboard/intel/baskingridge/chromeos.c</span><br><span>+++ b/src/mainboard/intel/baskingridge/chromeos.c</span><br><span>@@ -15,9 +15,11 @@</span><br><span> </span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> #include <southbridge/intel/lynxpoint/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>@@ -98,3 +100,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>index 0f672b6..5c55ed3 100644</span><br><span>--- a/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>+++ b/src/mainboard/samsung/lumpy/chromeos.c</span><br><span>@@ -15,10 +15,12 @@</span><br><span> </span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <northbridge/intel/sandybridge/sandybridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>@@ -150,3 +152,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>index 9c34995..5c5383f 100644</span><br><span>--- a/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>+++ b/src/mainboard/samsung/stumpy/chromeos.c</span><br><span>@@ -15,9 +15,11 @@</span><br><span> </span><br><span> #include <string.h></span><br><span> #include <bootmode.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> #include <southbridge/intel/bd82x6x/pch.h></span><br><span> #include <southbridge/intel/common/gpio.h></span><br><span> #include <vendorcode/google/chromeos/chromeos.h></span><br><span>@@ -147,3 +149,11 @@</span><br><span> {</span><br><span> chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(DEFAULT_PMBASE + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c</span><br><span>index dd74722..6e080a3 100644</span><br><span>--- a/src/security/vboot/vboot_logic.c</span><br><span>+++ b/src/security/vboot/vboot_logic.c</span><br><span>@@ -310,7 +310,6 @@</span><br><span> * does verification of memory init and thus must ensure it resumes with</span><br><span> * the same slot that it booted from. */</span><br><span> if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&</span><br><span style="color: hsl(0, 100%, 40%);">- IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) &&</span><br><span> vboot_platform_is_resuming())</span><br><span> ctx.flags |= VB2_CONTEXT_S3_RESUME;</span><br><span> </span><br><span>diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c</span><br><span>index 30e6d1d..dab5be3 100644</span><br><span>--- a/src/soc/intel/baytrail/pmutil.c</span><br><span>+++ b/src/soc/intel/baytrail/pmutil.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> */</span><br><span> </span><br><span> #include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <cbmem.h></span><br><span> #include <console/console.h></span><br><span>@@ -23,6 +24,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pmc.h></span><br><span> #include <security/vboot/vbnv.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> #if defined(__SIMPLE_DEVICE__)</span><br><span> </span><br><span>@@ -384,3 +386,11 @@</span><br><span> {</span><br><span> return rtc_failure();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c</span><br><span>index 00284d1..85384a61 100644</span><br><span>--- a/src/soc/intel/braswell/pmutil.c</span><br><span>+++ b/src/soc/intel/braswell/pmutil.c</span><br><span>@@ -14,6 +14,7 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <cbmem.h></span><br><span> #include <console/console.h></span><br><span>@@ -24,6 +25,7 @@</span><br><span> #include <soc/pm.h></span><br><span> #include <stdint.h></span><br><span> #include <security/vboot/vbnv.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> #if defined(__SIMPLE_DEVICE__)</span><br><span> </span><br><span>@@ -380,3 +382,11 @@</span><br><span> {</span><br><span> return rtc_failure();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c</span><br><span>index 3899130..e19025b 100644</span><br><span>--- a/src/soc/intel/broadwell/pmutil.c</span><br><span>+++ b/src/soc/intel/broadwell/pmutil.c</span><br><span>@@ -18,6 +18,7 @@</span><br><span> * and the differences between PCH variants.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span> #include <arch/io.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span>@@ -29,6 +30,7 @@</span><br><span> #include <soc/pm.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <security/vboot/vbnv.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <security/vboot/vboot_common.h></span><br><span> </span><br><span> /* Print status bits with descriptive names */</span><br><span> static void print_status_bits(u32 status, const char *bit_names[])</span><br><span>@@ -473,3 +475,11 @@</span><br><span> {</span><br><span> return rtc_failure();</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int vboot_platform_is_resuming(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS))</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29060">change 29060</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29060"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 </div>
<div style="display:none"> Gerrit-Change-Number: 29060 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Joel Kitching <kitching@google.com> </div>