[coreboot-gerrit] Change in coreboot[master]: mb/cavium/cn8100_sff_evb: Only expose two UARTs
Philipp Deppenwiese (Code Review)
gerrit at coreboot.org
Thu Oct 11 02:58:36 CEST 2018
Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28986 )
Change subject: mb/cavium/cn8100_sff_evb: Only expose two UARTs
......................................................................
mb/cavium/cn8100_sff_evb: Only expose two UARTs
Only two UARTs are connected to the FTDI UART USB chip.
Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
Reviewed-on: https://review.coreboot.org/28986
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
---
M src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Philipp Deppenwiese: Looks good to me, approved
diff --git a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
index 3398e9a..00be155 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
+++ b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb
@@ -93,11 +93,11 @@
end
chip soc/cavium/common/pci
register "secure" = "1"
- device pci 08.2 on end # UUA2
+ device pci 08.2 off end # UUA2
end
chip soc/cavium/common/pci
register "secure" = "1"
- device pci 08.3 on end # UUA3
+ device pci 08.3 off end # UUA3
end
chip soc/cavium/common/pci
register "secure" = "1"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a
Gerrit-Change-Number: 28986
Gerrit-PatchSet: 2
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
Gerrit-Reviewer: David Hendricks <david.hendricks at gmail.com>
Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus at 9elements.com>
Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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