[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Don't set FPU state to "dirty"

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28987


Change subject: arch/riscv: Don't set FPU state to "dirty"
......................................................................

arch/riscv: Don't set FPU state to "dirty"

Quoting from the RISC-V Privileged Architecture manual version 1.10,
chapter 3.1.11:

    The FS and XS fields use the same status encoding as shown in Table
    3.3, with the four possible status values being Off, Initial, Clean,
    and Dirty.

    Status   FS Meaning    XS Meaning
        0    Off           All off
        1    Initial       None dirty of clean, some on
        2    Clean         None dirty, some clean
        3    Dirty         Some dirty

Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/arch/riscv/virtual_memory.c
1 file changed, 0 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/28987/1

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index d9bae2a..506a047 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -40,11 +40,6 @@
 
 void mstatus_init(void)
 {
-	uintptr_t ms = 0;
-
-	ms = INSERT_FIELD(ms, MSTATUS_FS, 3);
-	write_csr(mstatus, ms);
-
 	// clear any pending timer interrupts.
 	clear_csr(mip,  MIP_STIP | MIP_SSIP);
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37
Gerrit-Change-Number: 28987
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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