[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Remove hudson register definitions

Marshall Dawson (Code Review) gerrit at coreboot.org
Thu Oct 11 01:14:13 CEST 2018


Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29008


Change subject: amd/stoneyridge: Remove hudson register definitions
......................................................................

amd/stoneyridge: Remove hudson register definitions

Delete artifacts remaining from the original "hudson" and "yangtze"
controller hub designs.

Husdon devices had a configurable AcpiMmio base address, and a selection
for I/O vs. MMIO decode.  Modern products are fixed at 0xfed80000 in MMIO.

Remove the flash control register definitions for the old generations.

The manual reset register appears to not function as hudson.

PMIO_DEBUG is named differently now, and not used, so remove its
definition too.

Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
1 file changed, 0 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29008/1

diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index a3c4c7c..e7a8cc3 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -40,7 +40,6 @@
 #define PM_PCI_CTRL			0x08
 #define   FORCE_SLPSTATE_RETRY		BIT(25)
 #define   FORCE_STPCLK_RETRY		BIT(24)
-#define PM_ACPI_MMIO_EN			0x24
 #define PM_SERIRQ_CONF			0x54
 #define   PM_SERIRQ_NUM_BITS_17		0x0000
 #define   PM_SERIRQ_NUM_BITS_18		0x0004
@@ -92,10 +91,6 @@
 #define PM_RST_CTRL1			0xbe
 #define   SLPTYPE_CONTROL_EN		BIT(5)
 #define PM_RST_STATUS			0xc0
-#define PM_PMIO_DEBUG			0xd2
-#define PM_MANUAL_RESET			0xd3
-#define PM_HUD_SD_FLASH_CTRL		0xe7
-#define PM_YANG_SD_FLASH_CTRL		0xe8
 #define PM_PCIB_CFG			0xea
 #define   PM_GENINT_DISABLE		BIT(0)
 #define PM_LPC_GATING			0xec

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de
Gerrit-Change-Number: 29008
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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