<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29008">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Remove hudson register definitions<br><br>Delete artifacts remaining from the original "hudson" and "yangtze"<br>controller hub designs.<br><br>Husdon devices had a configurable AcpiMmio base address, and a selection<br>for I/O vs. MMIO decode.  Modern products are fixed at 0xfed80000 in MMIO.<br><br>Remove the flash control register definitions for the old generations.<br><br>The manual reset register appears to not function as hudson.<br><br>PMIO_DEBUG is named differently now, and not used, so remove its<br>definition too.<br><br>Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>1 file changed, 0 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29008/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index a3c4c7c..e7a8cc3 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -40,7 +40,6 @@</span><br><span> #define PM_PCI_CTRL                       0x08</span><br><span> #define   FORCE_SLPSTATE_RETRY          BIT(25)</span><br><span> #define   FORCE_STPCLK_RETRY         BIT(24)</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_ACPI_MMIO_EN                  0x24</span><br><span> #define PM_SERIRQ_CONF                  0x54</span><br><span> #define   PM_SERIRQ_NUM_BITS_17         0x0000</span><br><span> #define   PM_SERIRQ_NUM_BITS_18               0x0004</span><br><span>@@ -92,10 +91,6 @@</span><br><span> #define PM_RST_CTRL1                     0xbe</span><br><span> #define   SLPTYPE_CONTROL_EN            BIT(5)</span><br><span> #define PM_RST_STATUS                 0xc0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_PMIO_DEBUG                       0xd2</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_MANUAL_RESET                     0xd3</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_HUD_SD_FLASH_CTRL                0xe7</span><br><span style="color: hsl(0, 100%, 40%);">-#define PM_YANG_SD_FLASH_CTRL               0xe8</span><br><span> #define PM_PCIB_CFG                     0xea</span><br><span> #define   PM_GENINT_DISABLE             BIT(0)</span><br><span> #define PM_LPC_GATING                 0xec</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29008">change 29008</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29008"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de </div>
<div style="display:none"> Gerrit-Change-Number: 29008 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>