[coreboot-gerrit] Change in coreboot[master]: Use macros instead of magic numbers
Peter Lemenkov (Code Review)
gerrit at coreboot.org
Tue Oct 9 13:17:43 CEST 2018
Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/28976
Change subject: Use macros instead of magic numbers
......................................................................
Use macros instead of magic numbers
Coreboot still uses magic numbers instead of macros in some Lenovo
mainboards. Let's use macros instead.
Also removed some board names from comments since these functions
sometimes are very similar, so no need to add extra difference between
them.
Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a
Signed-off-by: Peter Lemenkov <lemenkov at gmail.com>
---
M src/mainboard/lenovo/l520/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t530/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x201/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x230/romstage.c
8 files changed, 26 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28976/1
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index 0f6ffed..1122e1c 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -25,16 +25,21 @@
void pch_enable_lpc(void)
{
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
+ /* EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse, FDD, LPT */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ FDD_LPC_EN | LPT_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1611);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x040069);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x0c0701);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000000);
}
void mainboard_rcba_config(void)
{
- RCBA32(0x3414) = 0x00000000;
+ RCBA32(BUC) = 0;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, -1 },
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index 7e002d4..8447fef 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -32,18 +32,18 @@
void pch_enable_lpc(void)
{
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000);
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x00000);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */
pci_write_config32(
- PCI_DEV(0, 0x1f, 0), 0x98,
+ PCH_LPC_DEV, 0x98,
CONFIG_EC_BASE_ADDRESS | 1);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0);
+ pci_write_config16(PCH_LPC_DEV, 0xd8, 0xffc0);
/* Enable external USB port power. */
if (IS_ENABLED(CONFIG_USBDEBUG))
@@ -53,7 +53,7 @@
void mainboard_rcba_config(void)
{
/* Disable devices. */
- RCBA32(0x3414) = 0x00000020;
+ RCBA32(BUC) = 0x00000020;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 },
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 4fcd651..8769f01 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -63,7 +63,7 @@
void pch_enable_lpc(void)
{
- /* T520 EC Decode Range Port60/64, Port62/66 */
+ /* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 88e07c1..ac8c514 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -55,7 +55,7 @@
void pch_enable_lpc(void)
{
- /* X230 EC Decode Range Port60/64, Port62/66 */
+ /* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index a34d1db..bd1c6a3 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -36,7 +36,7 @@
void pch_enable_lpc(void)
{
- /* X230 EC Decode Range Port60/64, Port62/66 */
+ /* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 8752949..b6efbd7 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -45,7 +45,7 @@
static void pch_enable_lpc(void)
{
- /* X201 EC Decode Range Port60/64, Port62/66 */
+ /* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 96e0284..fb25f79 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -36,7 +36,7 @@
void pch_enable_lpc(void)
{
- /* X230 EC Decode Range Port60/64, Port62/66 */
+ /* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 1ddaedf..91b90d2 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -34,7 +34,7 @@
void pch_enable_lpc(void)
{
- /* X230 EC Decode Range Port60/64, Port62/66 */
+ /* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
--
To view, visit https://review.coreboot.org/28976
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a
Gerrit-Change-Number: 28976
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Lemenkov <lemenkov at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181009/63b2a850/attachment-0001.html>
More information about the coreboot-gerrit
mailing list