[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Disable Legacy PME for Root ports

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28947


Change subject: soc/intel/cannonlake: Disable Legacy PME for Root ports
......................................................................

soc/intel/cannonlake: Disable Legacy PME for Root ports

Legacy PME are enabled by default in FSP-S UPD. This patch to override
root port legacy pme upd policy from coreboot.

BUG=b:113083354
BRANCH=none
TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase

Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/28947/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index cbc97b2..d5233ed 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -129,6 +129,9 @@
 	/* S0ix */
 	params->PchPmSlpS0Enable = config->s0ix_enable;
 
+	/* disable Legacy PME */
+	memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
 	/* USB */
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 		params->PortUsb20Enable[i] = config->usb2_ports[i].enable;

-- 
To view, visit https://review.coreboot.org/28947
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb
Gerrit-Change-Number: 28947
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181006/28752c64/attachment-0001.html>