[coreboot-gerrit] Change in coreboot[master]: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS

[Nick Vaccaro (Code Review)]

Hello Duncan Laurie, Lijian Zhao, build bot (Jenkins), Furquan Shaikh, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/28932

to look at the new patch set (#2).

Change subject: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS
......................................................................

acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS

The logic for setting PCIEXP_WAKE_DIS bit is backwards. According
to EDS, PCIEXP_WAKE_DIS bit should be set to disable "the inputs to
the PCIEXP_WAKE_STS bit in the PM1 Status register from waking the
system", but the logic was setting that bit if DSX_EN_WAKE_PIN is
enabled, not disabled.  This was causing spurious wake issues on
nocturne.

Changed logic to set the PCIEXP_WAKE_DIS (PCIEXPWAK_STS) bit if
DSX_EN_WAKE_PIN is not defined in deep_sx_config register in
devicetree.cb.

BUG=b:111683988
TEST="emerge-nocturne coreboot chromeos-bootimage', flash build
onto nocturne, boot nocturne, and verify that pulling WAKE# pin
low does not wake the system.

Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da
Signed-off-by: Nick Vaccaro <nvaccaro at google.com>
---
M src/soc/intel/skylake/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28932/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da
Gerrit-Change-Number: 28932
Gerrit-PatchSet: 2
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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