[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions.
build bot (Jenkins) (Code Review)
gerrit at coreboot.org
Wed Oct 3 07:57:31 CEST 2018
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28890 )
Change subject: soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions.
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Patch Set 1:
(186 comments)
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c
File src/soc/intel/cannonlake/gpio.c:
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@150
PS1, Line 150: INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP_A */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@150
PS1, Line 150: INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP_A */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@151
PS1, Line 151: INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP_B */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@151
PS1, Line 151: INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP_B */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@155
PS1, Line 155: INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@155
PS1, Line 155: INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@156
PS1, Line 156: INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP_D */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@156
PS1, Line 156: INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP_D */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@157
PS1, Line 157: INTEL_GPP(GPP_C0, GPP_G0, GPP_G7), /* GPP_G */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@157
PS1, Line 157: INTEL_GPP(GPP_C0, GPP_G0, GPP_G7), /* GPP_G */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@161
PS1, Line 161: INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@161
PS1, Line 161: INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@165
PS1, Line 165: INTEL_GPP(GPP_K0, GPP_K0, GPP_K23), /* GPP_K*/
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@165
PS1, Line 165: INTEL_GPP(GPP_K0, GPP_K0, GPP_K23), /* GPP_K*/
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@166
PS1, Line 166: INTEL_GPP(GPP_K0, GPP_H0, GPP_H23), /* GPP_H */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@166
PS1, Line 166: INTEL_GPP(GPP_K0, GPP_H0, GPP_H23), /* GPP_H */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@167
PS1, Line 167: INTEL_GPP(GPP_K0, GPP_E0, GPP_E12), /* GPP_E */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@167
PS1, Line 167: INTEL_GPP(GPP_K0, GPP_E0, GPP_E12), /* GPP_E */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@168
PS1, Line 168: INTEL_GPP(GPP_K0, GPP_F0, GPP_F23), /* GPP_F */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@168
PS1, Line 168: INTEL_GPP(GPP_K0, GPP_F0, GPP_F23), /* GPP_F */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@172
PS1, Line 172: INTEL_GPP(GPP_I0, GPP_I0, GPP_I14), /* GPP_I */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@172
PS1, Line 172: INTEL_GPP(GPP_I0, GPP_I0, GPP_I14), /* GPP_I */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@173
PS1, Line 173: INTEL_GPP(GPP_I0, GPP_J0, GPP_J11), /* GPP_J */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@173
PS1, Line 173: INTEL_GPP(GPP_I0, GPP_J0, GPP_J11), /* GPP_J */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@177
PS1, Line 177: { /* GPP A, B */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@177
PS1, Line 177: { /* GPP A, B */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@178
PS1, Line 178: .port = PID_GPIOCOM0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@178
PS1, Line 178: .port = PID_GPIOCOM0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@179
PS1, Line 179: .first_pad = GPP_A0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@179
PS1, Line 179: .first_pad = GPP_A0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@180
PS1, Line 180: .last_pad = GPP_B23,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@180
PS1, Line 180: .last_pad = GPP_B23,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@181
PS1, Line 181: .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@181
PS1, Line 181: .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@182
PS1, Line 182: .pad_cfg_base = PAD_CFG_BASE,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@182
PS1, Line 182: .pad_cfg_base = PAD_CFG_BASE,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@183
PS1, Line 183: .host_own_reg_0 = HOSTSW_OWN_REG_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@183
PS1, Line 183: .host_own_reg_0 = HOSTSW_OWN_REG_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@184
PS1, Line 184: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@184
PS1, Line 184: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@185
PS1, Line 185: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@185
PS1, Line 185: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@186
PS1, Line 186: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@186
PS1, Line 186: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@187
PS1, Line 187: .name = "GPP_AB",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@187
PS1, Line 187: .name = "GPP_AB",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@188
PS1, Line 188: .acpi_path = "\\_SB.PCI0.GPIO",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@188
PS1, Line 188: .acpi_path = "\\_SB.PCI0.GPIO",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@189
PS1, Line 189: .reset_map = rst_map_com0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@189
PS1, Line 189: .reset_map = rst_map_com0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@190
PS1, Line 190: .num_reset_vals = ARRAY_SIZE(rst_map_com0),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@190
PS1, Line 190: .num_reset_vals = ARRAY_SIZE(rst_map_com0),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@191
PS1, Line 191: .groups = cnl_community0_groups,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@191
PS1, Line 191: .groups = cnl_community0_groups,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@192
PS1, Line 192: .num_groups = ARRAY_SIZE(cnl_community0_groups),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@192
PS1, Line 192: .num_groups = ARRAY_SIZE(cnl_community0_groups),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@193
PS1, Line 193: }, { /* GPP C, D, G */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@193
PS1, Line 193: }, { /* GPP C, D, G */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@194
PS1, Line 194: .port = PID_GPIOCOM1,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@194
PS1, Line 194: .port = PID_GPIOCOM1,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@195
PS1, Line 195: .first_pad = GPP_C0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@195
PS1, Line 195: .first_pad = GPP_C0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@196
PS1, Line 196: .last_pad = GPP_G7,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@196
PS1, Line 196: .last_pad = GPP_G7,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@197
PS1, Line 197: .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@197
PS1, Line 197: .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@198
PS1, Line 198: .pad_cfg_base = PAD_CFG_BASE,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@198
PS1, Line 198: .pad_cfg_base = PAD_CFG_BASE,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@199
PS1, Line 199: .host_own_reg_0 = HOSTSW_OWN_REG_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@199
PS1, Line 199: .host_own_reg_0 = HOSTSW_OWN_REG_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@200
PS1, Line 200: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@200
PS1, Line 200: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@201
PS1, Line 201: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@201
PS1, Line 201: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@202
PS1, Line 202: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@202
PS1, Line 202: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@203
PS1, Line 203: .name = "GPP_CDG",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@203
PS1, Line 203: .name = "GPP_CDG",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@204
PS1, Line 204: .acpi_path = "\\_SB.PCI0.GPIO",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@204
PS1, Line 204: .acpi_path = "\\_SB.PCI0.GPIO",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@205
PS1, Line 205: .reset_map = rst_map,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@205
PS1, Line 205: .reset_map = rst_map,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@206
PS1, Line 206: .num_reset_vals = ARRAY_SIZE(rst_map),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@206
PS1, Line 206: .num_reset_vals = ARRAY_SIZE(rst_map),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@207
PS1, Line 207: .groups = cnl_community1_groups,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@207
PS1, Line 207: .groups = cnl_community1_groups,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@208
PS1, Line 208: .num_groups = ARRAY_SIZE(cnl_community1_groups),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@208
PS1, Line 208: .num_groups = ARRAY_SIZE(cnl_community1_groups),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@209
PS1, Line 209: }, { /* GPD */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@209
PS1, Line 209: }, { /* GPD */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@210
PS1, Line 210: .port = PID_GPIOCOM2,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@210
PS1, Line 210: .port = PID_GPIOCOM2,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@211
PS1, Line 211: .first_pad = GPD0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@211
PS1, Line 211: .first_pad = GPD0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@212
PS1, Line 212: .last_pad = GPD11,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@212
PS1, Line 212: .last_pad = GPD11,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@213
PS1, Line 213: .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@213
PS1, Line 213: .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@214
PS1, Line 214: .pad_cfg_base = PAD_CFG_BASE,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@214
PS1, Line 214: .pad_cfg_base = PAD_CFG_BASE,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@215
PS1, Line 215: .host_own_reg_0 = HOSTSW_OWN_REG_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@215
PS1, Line 215: .host_own_reg_0 = HOSTSW_OWN_REG_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@216
PS1, Line 216: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@216
PS1, Line 216: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@217
PS1, Line 217: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@217
PS1, Line 217: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@218
PS1, Line 218: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@218
PS1, Line 218: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@219
PS1, Line 219: .name = "GPD",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@219
PS1, Line 219: .name = "GPD",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@220
PS1, Line 220: .acpi_path = "\\_SB.PCI0.GPIO",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@220
PS1, Line 220: .acpi_path = "\\_SB.PCI0.GPIO",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@221
PS1, Line 221: .reset_map = rst_map,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@221
PS1, Line 221: .reset_map = rst_map,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@222
PS1, Line 222: .num_reset_vals = ARRAY_SIZE(rst_map),
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@222
PS1, Line 222: .num_reset_vals = ARRAY_SIZE(rst_map),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@223
PS1, Line 223: .groups = cnl_community2_groups,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@223
PS1, Line 223: .groups = cnl_community2_groups,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@224
PS1, Line 224: .num_groups = ARRAY_SIZE(cnl_community2_groups),
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@224
PS1, Line 224: .num_groups = ARRAY_SIZE(cnl_community2_groups),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@225
PS1, Line 225: }, { /* GPP K, H, E, F */
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@225
PS1, Line 225: }, { /* GPP K, H, E, F */
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@226
PS1, Line 226: .port = PID_GPIOCOM3,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@226
PS1, Line 226: .port = PID_GPIOCOM3,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@227
PS1, Line 227: .first_pad = GPP_K0,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@227
PS1, Line 227: .first_pad = GPP_K0,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@228
PS1, Line 228: .last_pad = GPP_F23,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@228
PS1, Line 228: .last_pad = GPP_F23,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@229
PS1, Line 229: .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@229
PS1, Line 229: .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@230
PS1, Line 230: .pad_cfg_base = PAD_CFG_BASE,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@230
PS1, Line 230: .pad_cfg_base = PAD_CFG_BASE,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@231
PS1, Line 231: .host_own_reg_0 = HOSTSW_OWN_REG_0,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@231
PS1, Line 231: .host_own_reg_0 = HOSTSW_OWN_REG_0,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@232
PS1, Line 232: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@232
PS1, Line 232: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@233
PS1, Line 233: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@233
PS1, Line 233: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@234
PS1, Line 234: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@234
PS1, Line 234: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@235
PS1, Line 235: .name = "GPP_KHEF",
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@235
PS1, Line 235: .name = "GPP_KHEF",
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@236
PS1, Line 236: .acpi_path = "\\_SB.PCI0.GPIO",
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@236
PS1, Line 236: .acpi_path = "\\_SB.PCI0.GPIO",
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@237
PS1, Line 237: .reset_map = rst_map,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@237
PS1, Line 237: .reset_map = rst_map,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@238
PS1, Line 238: .num_reset_vals = ARRAY_SIZE(rst_map),
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@238
PS1, Line 238: .num_reset_vals = ARRAY_SIZE(rst_map),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@239
PS1, Line 239: .groups = cnl_community3_groups,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@239
PS1, Line 239: .groups = cnl_community3_groups,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@240
PS1, Line 240: .num_groups = ARRAY_SIZE(cnl_community3_groups),
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@240
PS1, Line 240: .num_groups = ARRAY_SIZE(cnl_community3_groups),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@241
PS1, Line 241: }, { /* GPP I, J */
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@241
PS1, Line 241: }, { /* GPP I, J */
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@242
PS1, Line 242: .port = PID_GPIOCOM4,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@242
PS1, Line 242: .port = PID_GPIOCOM4,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@243
PS1, Line 243: .first_pad = GPP_I0,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@243
PS1, Line 243: .first_pad = GPP_I0,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@244
PS1, Line 244: .last_pad = GPP_J11,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@244
PS1, Line 244: .last_pad = GPP_J11,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@245
PS1, Line 245: .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@245
PS1, Line 245: .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@246
PS1, Line 246: .pad_cfg_base = PAD_CFG_BASE,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@246
PS1, Line 246: .pad_cfg_base = PAD_CFG_BASE,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@247
PS1, Line 247: .host_own_reg_0 = HOSTSW_OWN_REG_0,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@247
PS1, Line 247: .host_own_reg_0 = HOSTSW_OWN_REG_0,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@248
PS1, Line 248: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@248
PS1, Line 248: .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@249
PS1, Line 249: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@249
PS1, Line 249: .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@250
PS1, Line 250: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@250
PS1, Line 250: .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@251
PS1, Line 251: .name = "GPP_IJ",
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@251
PS1, Line 251: .name = "GPP_IJ",
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@252
PS1, Line 252: .acpi_path = "\\_SB.PCI0.GPIO",
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@252
PS1, Line 252: .acpi_path = "\\_SB.PCI0.GPIO",
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@253
PS1, Line 253: .reset_map = rst_map,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@253
PS1, Line 253: .reset_map = rst_map,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@254
PS1, Line 254: .num_reset_vals = ARRAY_SIZE(rst_map),
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@254
PS1, Line 254: .num_reset_vals = ARRAY_SIZE(rst_map),
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@255
PS1, Line 255: .groups = cnl_community4_groups,
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@255
PS1, Line 255: .groups = cnl_community4_groups,
please, no spaces at the start of a line
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@256
PS1, Line 256: .num_groups = ARRAY_SIZE(cnl_community4_groups),
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@256
PS1, Line 256: .num_groups = ARRAY_SIZE(cnl_community4_groups),
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https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@257
PS1, Line 257: }
code indent should use tabs where possible
https://review.coreboot.org/#/c/28890/1/src/soc/intel/cannonlake/gpio.c@257
PS1, Line 257: }
please, no spaces at the start of a line
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Gerrit-Change-Number: 28890
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Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
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