[coreboot-gerrit] Change in coreboot[master]: mb/emulation/spike-riscv: Implement mtime_init

Jonathan Neuschäfer (Code Review) gerrit at coreboot.org
Tue Oct 2 13:15:39 CEST 2018


Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/28873

to look at the new patch set (#2).

Change subject: mb/emulation/spike-riscv: Implement mtime_init
......................................................................

mb/emulation/spike-riscv: Implement mtime_init

This patch lets spike boot to "Payload not loaded" again.

Because soc/ucb/riscv/ is does not represent a real SoC, but is a dummy
directory for emulators, and different emulators might have different
memory maps, I moved mtime_init to the mainboard-specific directories
for Spike and QEMU.

Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/mainboard/emulation/qemu-riscv/Makefile.inc
R src/mainboard/emulation/qemu-riscv/mtime.c
M src/mainboard/emulation/spike-riscv/Makefile.inc
A src/mainboard/emulation/spike-riscv/clint.c
M src/soc/ucb/riscv/Makefile.inc
5 files changed, 30 insertions(+), 2 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28873/2
-- 
To view, visit https://review.coreboot.org/28873
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2
Gerrit-Change-Number: 28873
Gerrit-PatchSet: 2
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181002/134721b7/attachment.html>


More information about the coreboot-gerrit mailing list