[coreboot-gerrit] Change in coreboot[master]: mb/emulation/spike-riscv: Implement mtime_init

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28873


Change subject: mb/emulation/spike-riscv: Implement mtime_init
......................................................................

mb/emulation/spike-riscv: Implement mtime_init

This patch lets spike boot to "Payload not loaded" again.

Because soc/ucb/riscv/ is does not represent a real SoC, but is a dummy
directory for emulators, and different emulators might have different
memory maps, I moved mtime_init to mb/emulation/spike-riscv.

Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/mainboard/emulation/spike-riscv/Makefile.inc
R src/mainboard/emulation/spike-riscv/clint.c
M src/soc/ucb/riscv/Makefile.inc
3 files changed, 7 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28873/1

diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc
index 36f1fca..38977b6 100644
--- a/src/mainboard/emulation/spike-riscv/Makefile.inc
+++ b/src/mainboard/emulation/spike-riscv/Makefile.inc
@@ -14,11 +14,13 @@
 
 bootblock-y += uart.c
 bootblock-y += rom_media.c
+bootblock-y += clint.c
 romstage-y += romstage.c
 romstage-y += uart.c
 romstage-y += rom_media.c
 ramstage-y += uart.c
 ramstage-y += rom_media.c
+ramstage-y += clint.c
 
 bootblock-y += memlayout.ld
 romstage-y += memlayout.ld
diff --git a/src/soc/ucb/riscv/mtime.c b/src/mainboard/emulation/spike-riscv/clint.c
similarity index 76%
rename from src/soc/ucb/riscv/mtime.c
rename to src/mainboard/emulation/spike-riscv/clint.c
index f8c2717..7ad3f5a 100644
--- a/src/soc/ucb/riscv/mtime.c
+++ b/src/mainboard/emulation/spike-riscv/clint.c
@@ -15,8 +15,12 @@
 
 #include <mcall.h>
 
-/* FIXME: This is an empty implementation, please improve */
+#define SPIKE_CLINT_BASE	0x02000000
+
 /* This function is used to initialize HLS()->time/HLS()->timecmp  */
 void mtime_init(void)
 {
+	long hart_id = read_csr(mhartid);
+	HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8);
+	HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id);
 }
diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc
index a10f3aa..1072a2b 100644
--- a/src/soc/ucb/riscv/Makefile.inc
+++ b/src/soc/ucb/riscv/Makefile.inc
@@ -1,8 +1,6 @@
 ifeq ($(CONFIG_SOC_UCB_RISCV),y)
 
-bootblock-y += mtime.c
 romstage-y += cbmem.c
 ramstage-y += cbmem.c
-ramstage-y += mtime.c
 
 endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2
Gerrit-Change-Number: 28873
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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