[coreboot-gerrit] Change in coreboot[master]: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue Oct 2 08:45:24 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28871
Change subject: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
......................................................................
src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/intel/fsp_model_206ax/finalize.c
M src/cpu/intel/fsp_model_206ax/model_206ax.h
M src/cpu/intel/fsp_model_406dx/model_406dx.h
M src/cpu/intel/haswell/finalize.c
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/model_106cx/model_106cx_init.c
M src/cpu/intel/model_2065x/finalize.c
M src/cpu/intel/model_206ax/finalize.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/cpu/intel/model_6ex/model_6ex_init.c
M src/cpu/intel/model_6fx/model_6fx_init.c
M src/include/cpu/intel/speedstep.h
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/baytrail/cpu.c
M src/soc/intel/baytrail/include/soc/msr.h
M src/soc/intel/braswell/cpu.c
M src/soc/intel/braswell/include/soc/msr.h
M src/soc/intel/broadwell/cpu.c
M src/soc/intel/broadwell/include/soc/msr.h
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/denverton_ns/include/soc/msr.h
M src/soc/intel/fsp_baytrail/cpu.c
M src/soc/intel/fsp_baytrail/include/soc/msr.h
25 files changed, 38 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28871/1
diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c
index 2d5973b..d143497 100644
--- a/src/cpu/intel/fsp_model_206ax/finalize.c
+++ b/src/cpu/intel/fsp_model_206ax/finalize.c
@@ -45,7 +45,7 @@
void intel_model_206ax_finalize_smm(void)
{
/* Lock C-State MSR */
- msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h
index e65b370..1af54df 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h
@@ -43,7 +43,7 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_MISC_PWR_MGMT 0x1aa
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h
index 87daeac..c40b597 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h
@@ -45,7 +45,7 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_MISC_PWR_MGMT 0x1aa
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index ce22e62..b170215 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -48,7 +48,7 @@
{
#if 0
/* Lock C-State MSR */
- msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 8498c1a..8e59ccb 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -58,7 +58,7 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_MISC_PWR_MGMT 0x1aa
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 24de43e..bba1410 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -486,7 +486,7 @@
{
msr_t msr;
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 30); // Package c-state Undemotion Enable
msr.lo |= (1 << 29); // Package c-state Demotion Enable
msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
@@ -495,7 +495,7 @@
msr.lo |= (1 << 25); // C3 Auto Demotion Enable
msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
/* The deepest package c-state defaults to factory-configured value. */
- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
msr.lo &= ~0xffff;
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 0d9169b..f304b94 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -63,7 +63,7 @@
const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo |= (1 << 8);
if (quad)
@@ -79,7 +79,7 @@
msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */
if (c6)
msr.lo |= (1 << 25);
- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE */
msr.hi = 0;
@@ -129,10 +129,10 @@
wrmsr(IA32_PERF_CTL, msr);
}
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo &= ~(1 << 11); /* Enable hw coordination. */
msr.lo |= (1 << 15); /* Lock config until next reset. */
- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
}
#define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x))
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index dd7bbc8..780575a 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -32,14 +32,14 @@
{
msr_t msr;
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // Lock configuration
msr.lo |= (1 << 10); // redirect IO-based CState transition requests to
// MWAIT
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index 8425f6a..08541c0 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -46,7 +46,7 @@
void intel_model_2065x_finalize_smm(void)
{
/* Lock C-State MSR */
- msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 7d3cc2e..5c69ffc 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -46,7 +46,7 @@
void intel_model_206ax_finalize_smm(void)
{
/* Lock C-State MSR */
- msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 3cc8d82..ece8971 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -252,14 +252,14 @@
{
msr_t msr;
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
msr.lo |= (1 << 27); // C3 Auto Undemotion Enable
msr.lo |= (1 << 26); // C1 Auto Demotion Enable
msr.lo |= (1 << 25); // C3 Auto Demotion Enable
msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
msr.lo |= 7; // No package C-state limit
- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR);
msr.lo &= ~0x7ffff;
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 96830c4..68be567 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -33,7 +33,7 @@
{
msr_t msr;
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // config lock until next reset
msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
@@ -43,7 +43,7 @@
msr.lo &= ~7;
msr.lo |= HIGHEST_CLEVEL; // support at most C3
- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index a1433f6..642201c 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -33,7 +33,7 @@
{
msr_t msr;
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // config lock until next reset
msr.lo |= (1 << 14); // Deeper Sleep
msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
@@ -44,7 +44,7 @@
msr.lo &= ~7;
msr.lo |= HIGHEST_CLEVEL; // support at most C3
- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 4b556b7..5390781 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -43,7 +43,7 @@
#define MSR_EBC_FREQUENCY_ID 0x2c
#define MSR_FSB_FREQ 0xcd
#define MSR_FSB_CLOCK_VCC 0xce
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_BASE_ADDR 0xe3
#define MSR_PMG_IO_CAPTURE_ADDR 0xe4
#define MSR_EXTENDED_CONFIG 0xee
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index caa3bbf..e745996 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -47,7 +47,7 @@
static const struct reg_script core_msr_script[] = {
#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
/* Enable C-state and IO/MWAIT redirect */
- REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL,
+ REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL,
(PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
| IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)),
/* Power Management I/O base address for I/O trapping to C-states */
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c
index 618430b..9bbeafb 100644
--- a/src/soc/intel/baytrail/cpu.c
+++ b/src/soc/intel/baytrail/cpu.c
@@ -35,7 +35,7 @@
/* Core level MSRs */
const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
- REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
+ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
REG_MSR_RMW(MSR_POWER_MISC,
~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
/* Disable C1E */
diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h
index 689d4d5..b332478 100644
--- a/src/soc/intel/baytrail/include/soc/msr.h
+++ b/src/soc/intel/baytrail/include/soc/msr.h
@@ -19,7 +19,7 @@
#define MSR_IA32_PLATFORM_ID 0x17
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd
#define MSR_PLATFORM_INFO 0xce
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define SINGLE_PCTL (1 << 11)
#define MSR_POWER_MISC 0x120
#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 85b04ac..6ed12af 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -36,7 +36,7 @@
/* Core level MSRs */
static const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
- REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
+ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
REG_MSR_RMW(MSR_POWER_MISC,
~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
/* Disable C1E */
diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h
index 47e9bcd..1a79b2f 100644
--- a/src/soc/intel/braswell/include/soc/msr.h
+++ b/src/soc/intel/braswell/include/soc/msr.h
@@ -21,7 +21,7 @@
#define MSR_IA32_BIOS_SIGN_ID 0x8B
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd
#define MSR_PLATFORM_INFO 0xce
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define SINGLE_PCTL (1 << 11)
#define MSR_POWER_MISC 0x120
#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index ee1fd52..3ef0d72 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -394,7 +394,7 @@
{
msr_t msr;
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 31); // Timed MWAIT Enable
msr.lo |= (1 << 30); // Package c-state Undemotion Enable
msr.lo |= (1 << 29); // Package c-state Demotion Enable
@@ -404,7 +404,7 @@
msr.lo |= (1 << 25); // C3 Auto Demotion Enable
msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
/* The deepest package c-state defaults to factory-configured value. */
- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
msr = rdmsr(MSR_MISC_PWR_MGMT);
msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index 41ce17c..c2a939e 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -23,7 +23,7 @@
#define CPUID_SMX (1 << 6)
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_FEATURE_CONFIG 0x13c
#define SMM_MCA_CAP_MSR 0x17d
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index e1fc431..154f03b 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -25,14 +25,14 @@
#define SGX_GLOBAL_ENABLE (1 << 18)
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PLATFORM_INFO 0xce
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
-/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
+/* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
#define PKG_C_STATE_LIMIT_C2_MASK 0x2
-/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
+/* Set MSR_PKG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
#define CORE_C_STATE_LIMIT_C10_MASK 0x70
-/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
+/* Set MSR_PKG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
#define IO_MWAIT_REDIRECT_MASK 0x400
-/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
+/* Set MSR_PKG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
#define CST_CFG_LOCK_MASK 0x8000
#define MSR_BIOS_UPGD_TRIG 0x7a
#define SGX_ACTIVATE_BIT (1)
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h
index 4d1ac70..a2a42f1 100644
--- a/src/soc/intel/denverton_ns/include/soc/msr.h
+++ b/src/soc/intel/denverton_ns/include/soc/msr.h
@@ -26,7 +26,7 @@
#define CPUID_SMX (1 << 6)
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_FEATURE_CONFIG 0x13c
#define SMM_MCA_CAP_MSR 0x17d
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index a69d046..89ea4c2 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -35,7 +35,7 @@
/* Core level MSRs */
static const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold */
- REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),
+ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),
/* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
REG_MSR_OR(MSR_POWER_MISC, 0x44),
diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h
index ea1d790..4435256 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/msr.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h
@@ -19,7 +19,7 @@
#define MSR_IA32_PLATFORM_ID 0x17
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd
#define MSR_PLATFORM_INFO 0xce
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_POWER_MISC 0x120
#define MSR_IA32_PERF_CTL 0x199
#define MSR_IA32_MISC_ENABLES 0x1a0
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Gerrit-Change-Number: 28871
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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