<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28871">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Fix MSR_PKG_CST_CONFIG_CONTROL register name<br><br>Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/fsp_model_206ax/finalize.c<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/finalize.c<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/haswell/haswell_init.c<br>M src/cpu/intel/model_1067x/model_1067x_init.c<br>M src/cpu/intel/model_106cx/model_106cx_init.c<br>M src/cpu/intel/model_2065x/finalize.c<br>M src/cpu/intel/model_206ax/finalize.c<br>M src/cpu/intel/model_206ax/model_206ax_init.c<br>M src/cpu/intel/model_6ex/model_6ex_init.c<br>M src/cpu/intel/model_6fx/model_6fx_init.c<br>M src/include/cpu/intel/speedstep.h<br>M src/soc/intel/apollolake/cpu.c<br>M src/soc/intel/baytrail/cpu.c<br>M src/soc/intel/baytrail/include/soc/msr.h<br>M src/soc/intel/braswell/cpu.c<br>M src/soc/intel/braswell/include/soc/msr.h<br>M src/soc/intel/broadwell/cpu.c<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/fsp_baytrail/cpu.c<br>M src/soc/intel/fsp_baytrail/include/soc/msr.h<br>25 files changed, 38 insertions(+), 38 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28871/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c</span><br><span>index 2d5973b..d143497 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/finalize.c</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/finalize.c</span><br><span>@@ -45,7 +45,7 @@</span><br><span> void intel_model_206ax_finalize_smm(void)</span><br><span> {</span><br><span> /* Lock C-State MSR */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);</span><br><span> </span><br><span> /* Lock AES-NI only if supported */</span><br><span> if (cpuid_ecx(1) & (1 << 25))</span><br><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index e65b370..1af54df 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -43,7 +43,7 @@</span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_PMG_IO_CAPTURE_BASE 0xe4</span><br><span> </span><br><span> #define MSR_MISC_PWR_MGMT 0x1aa</span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index 87daeac..c40b597 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -45,7 +45,7 @@</span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_PMG_IO_CAPTURE_BASE 0xe4</span><br><span> </span><br><span> #define MSR_MISC_PWR_MGMT 0x1aa</span><br><span>diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c</span><br><span>index ce22e62..b170215 100644</span><br><span>--- a/src/cpu/intel/haswell/finalize.c</span><br><span>+++ b/src/cpu/intel/haswell/finalize.c</span><br><span>@@ -48,7 +48,7 @@</span><br><span> {</span><br><span> #if 0</span><br><span> /* Lock C-State MSR */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);</span><br><span> </span><br><span> /* Lock AES-NI only if supported */</span><br><span> if (cpuid_ecx(1) & (1 << 25))</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index 8498c1a..8e59ccb 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -58,7 +58,7 @@</span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_PMG_IO_CAPTURE_BASE 0xe4</span><br><span> </span><br><span> #define MSR_MISC_PWR_MGMT 0x1aa</span><br><span>diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c</span><br><span>index 24de43e..bba1410 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell_init.c</span><br><span>+++ b/src/cpu/intel/haswell/haswell_init.c</span><br><span>@@ -486,7 +486,7 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);</span><br><span> msr.lo |= (1 << 30); // Package c-state Undemotion Enable</span><br><span> msr.lo |= (1 << 29); // Package c-state Demotion Enable</span><br><span> msr.lo |= (1 << 28); // C1 Auto Undemotion Enable</span><br><span>@@ -495,7 +495,7 @@</span><br><span> msr.lo |= (1 << 25); // C3 Auto Demotion Enable</span><br><span> msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection</span><br><span> /* The deepest package c-state defaults to factory-configured value. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);</span><br><span> </span><br><span> msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);</span><br><span> msr.lo &= ~0xffff;</span><br><span>diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>index 0d9169b..f304b94 100644</span><br><span>--- a/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>+++ b/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>@@ -63,7 +63,7 @@</span><br><span> </span><br><span> const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);</span><br><span> msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk</span><br><span> msr.lo |= (1 << 8);</span><br><span> if (quad)</span><br><span>@@ -79,7 +79,7 @@</span><br><span> msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */</span><br><span> if (c6)</span><br><span> msr.lo |= (1 << 25);</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);</span><br><span> </span><br><span> /* Set Processor MWAIT IO BASE */</span><br><span> msr.hi = 0;</span><br><span>@@ -129,10 +129,10 @@</span><br><span> wrmsr(IA32_PERF_CTL, msr);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);</span><br><span> msr.lo &= ~(1 << 11); /* Enable hw coordination. */</span><br><span> msr.lo |= (1 << 15); /* Lock config until next reset. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);</span><br><span> }</span><br><span> </span><br><span> #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x))</span><br><span>diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>index dd7bbc8..780575a 100644</span><br><span>--- a/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>+++ b/src/cpu/intel/model_106cx/model_106cx_init.c</span><br><span>@@ -32,14 +32,14 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);</span><br><span> msr.lo |= (1 << 15); // Lock configuration</span><br><span> msr.lo |= (1 << 10); // redirect IO-based CState transition requests to</span><br><span> // MWAIT</span><br><span> msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk</span><br><span> msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3</span><br><span> // TODO Do we want Deep C4 and Dynamic L2 shrinking?</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);</span><br><span> </span><br><span> /* Set Processor MWAIT IO BASE (P_BLK) */</span><br><span> msr.hi = 0;</span><br><span>diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c</span><br><span>index 8425f6a..08541c0 100644</span><br><span>--- a/src/cpu/intel/model_2065x/finalize.c</span><br><span>+++ b/src/cpu/intel/model_2065x/finalize.c</span><br><span>@@ -46,7 +46,7 @@</span><br><span> void intel_model_2065x_finalize_smm(void)</span><br><span> {</span><br><span> /* Lock C-State MSR */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);</span><br><span> </span><br><span> /* Lock AES-NI only if supported */</span><br><span> if (cpuid_ecx(1) & (1 << 25))</span><br><span>diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c</span><br><span>index 7d3cc2e..5c69ffc 100644</span><br><span>--- a/src/cpu/intel/model_206ax/finalize.c</span><br><span>+++ b/src/cpu/intel/model_206ax/finalize.c</span><br><span>@@ -46,7 +46,7 @@</span><br><span> void intel_model_206ax_finalize_smm(void)</span><br><span> {</span><br><span> /* Lock C-State MSR */</span><br><span style="color: hsl(0, 100%, 40%);">- msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);</span><br><span> </span><br><span> /* Lock AES-NI only if supported */</span><br><span> if (cpuid_ecx(1) & (1 << 25))</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>index 3cc8d82..ece8971 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax_init.c</span><br><span>@@ -252,14 +252,14 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);</span><br><span> msr.lo |= (1 << 28); // C1 Auto Undemotion Enable</span><br><span> msr.lo |= (1 << 27); // C3 Auto Undemotion Enable</span><br><span> msr.lo |= (1 << 26); // C1 Auto Demotion Enable</span><br><span> msr.lo |= (1 << 25); // C3 Auto Demotion Enable</span><br><span> msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection</span><br><span> msr.lo |= 7; // No package C-state limit</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);</span><br><span> </span><br><span> msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR);</span><br><span> msr.lo &= ~0x7ffff;</span><br><span>diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>index 96830c4..68be567 100644</span><br><span>--- a/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>+++ b/src/cpu/intel/model_6ex/model_6ex_init.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);</span><br><span> msr.lo |= (1 << 15); // config lock until next reset</span><br><span> msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States</span><br><span> msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk</span><br><span>@@ -43,7 +43,7 @@</span><br><span> msr.lo &= ~7;</span><br><span> msr.lo |= HIGHEST_CLEVEL; // support at most C3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);</span><br><span> </span><br><span> /* Set Processor MWAIT IO BASE (P_BLK) */</span><br><span> msr.hi = 0;</span><br><span>diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>index a1433f6..642201c 100644</span><br><span>--- a/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>+++ b/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>@@ -33,7 +33,7 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);</span><br><span> msr.lo |= (1 << 15); // config lock until next reset</span><br><span> msr.lo |= (1 << 14); // Deeper Sleep</span><br><span> msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States</span><br><span>@@ -44,7 +44,7 @@</span><br><span> msr.lo &= ~7;</span><br><span> msr.lo |= HIGHEST_CLEVEL; // support at most C3</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);</span><br><span> </span><br><span> /* Set Processor MWAIT IO BASE (P_BLK) */</span><br><span> msr.hi = 0;</span><br><span>diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h</span><br><span>index 4b556b7..5390781 100644</span><br><span>--- a/src/include/cpu/intel/speedstep.h</span><br><span>+++ b/src/include/cpu/intel/speedstep.h</span><br><span>@@ -43,7 +43,7 @@</span><br><span> #define MSR_EBC_FREQUENCY_ID 0x2c</span><br><span> #define MSR_FSB_FREQ 0xcd</span><br><span> #define MSR_FSB_CLOCK_VCC 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_PMG_IO_BASE_ADDR 0xe3</span><br><span> #define MSR_PMG_IO_CAPTURE_ADDR 0xe4</span><br><span> #define MSR_EXTENDED_CONFIG 0xee</span><br><span>diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c</span><br><span>index caa3bbf..e745996 100644</span><br><span>--- a/src/soc/intel/apollolake/cpu.c</span><br><span>+++ b/src/soc/intel/apollolake/cpu.c</span><br><span>@@ -47,7 +47,7 @@</span><br><span> static const struct reg_script core_msr_script[] = {</span><br><span> #if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)</span><br><span> /* Enable C-state and IO/MWAIT redirect */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL,</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL,</span><br><span> (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK</span><br><span> | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)),</span><br><span> /* Power Management I/O base address for I/O trapping to C-states */</span><br><span>diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c</span><br><span>index 618430b..9bbeafb 100644</span><br><span>--- a/src/soc/intel/baytrail/cpu.c</span><br><span>+++ b/src/soc/intel/baytrail/cpu.c</span><br><span>@@ -35,7 +35,7 @@</span><br><span> /* Core level MSRs */</span><br><span> const struct reg_script core_msr_script[] = {</span><br><span> /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),</span><br><span> REG_MSR_RMW(MSR_POWER_MISC,</span><br><span> ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),</span><br><span> /* Disable C1E */</span><br><span>diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>index 689d4d5..b332478 100644</span><br><span>--- a/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/baytrail/include/soc/msr.h</span><br><span>@@ -19,7 +19,7 @@</span><br><span> #define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define SINGLE_PCTL (1 << 11)</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span>diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c</span><br><span>index 85b04ac..6ed12af 100644</span><br><span>--- a/src/soc/intel/braswell/cpu.c</span><br><span>+++ b/src/soc/intel/braswell/cpu.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> /* Core level MSRs */</span><br><span> static const struct reg_script core_msr_script[] = {</span><br><span> /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),</span><br><span> REG_MSR_RMW(MSR_POWER_MISC,</span><br><span> ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),</span><br><span> /* Disable C1E */</span><br><span>diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h</span><br><span>index 47e9bcd..1a79b2f 100644</span><br><span>--- a/src/soc/intel/braswell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/braswell/include/soc/msr.h</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #define MSR_IA32_BIOS_SIGN_ID 0x8B</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define SINGLE_PCTL (1 << 11)</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define ENABLE_ULFM_AUTOCM_MASK (1 << 2)</span><br><span>diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c</span><br><span>index ee1fd52..3ef0d72 100644</span><br><span>--- a/src/soc/intel/broadwell/cpu.c</span><br><span>+++ b/src/soc/intel/broadwell/cpu.c</span><br><span>@@ -394,7 +394,7 @@</span><br><span> {</span><br><span> msr_t msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);</span><br><span> msr.lo |= (1 << 31); // Timed MWAIT Enable</span><br><span> msr.lo |= (1 << 30); // Package c-state Undemotion Enable</span><br><span> msr.lo |= (1 << 29); // Package c-state Demotion Enable</span><br><span>@@ -404,7 +404,7 @@</span><br><span> msr.lo |= (1 << 25); // C3 Auto Demotion Enable</span><br><span> msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection</span><br><span> /* The deepest package c-state defaults to factory-configured value. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);</span><br><span> </span><br><span> msr = rdmsr(MSR_MISC_PWR_MGMT);</span><br><span> msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index 41ce17c..c2a939e 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -23,7 +23,7 @@</span><br><span> #define CPUID_SMX (1 << 6)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_PMG_IO_CAPTURE_BASE 0xe4</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define SMM_MCA_CAP_MSR 0x17d</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index e1fc431..154f03b 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -25,14 +25,14 @@</span><br><span> #define SGX_GLOBAL_ENABLE (1 << 18)</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(0, 100%, 40%);">-/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */</span><br><span> #define PKG_C_STATE_LIMIT_C2_MASK 0x2</span><br><span style="color: hsl(0, 100%, 40%);">-/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set MSR_PKG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/</span><br><span> #define CORE_C_STATE_LIMIT_C10_MASK 0x70</span><br><span style="color: hsl(0, 100%, 40%);">-/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set MSR_PKG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */</span><br><span> #define IO_MWAIT_REDIRECT_MASK 0x400</span><br><span style="color: hsl(0, 100%, 40%);">-/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set MSR_PKG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */</span><br><span> #define CST_CFG_LOCK_MASK 0x8000</span><br><span> #define MSR_BIOS_UPGD_TRIG 0x7a</span><br><span> #define SGX_ACTIVATE_BIT (1)</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 4d1ac70..a2a42f1 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -26,7 +26,7 @@</span><br><span> #define CPUID_SMX (1 << 6)</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define PLATFORM_INFO_SET_TDP (1 << 29)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_PMG_IO_CAPTURE_BASE 0xe4</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span> #define SMM_MCA_CAP_MSR 0x17d</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>index a69d046..89ea4c2 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>+++ b/src/soc/intel/fsp_baytrail/cpu.c</span><br><span>@@ -35,7 +35,7 @@</span><br><span> /* Core level MSRs */</span><br><span> static const struct reg_script core_msr_script[] = {</span><br><span> /* Dynamic L2 shrink enable and threshold */</span><br><span style="color: hsl(0, 100%, 40%);">- REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),</span><br><span style="color: hsl(120, 100%, 40%);">+ REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),</span><br><span> /* Disable C1E */</span><br><span> REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),</span><br><span> REG_MSR_OR(MSR_POWER_MISC, 0x44),</span><br><span>diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>index ea1d790..4435256 100644</span><br><span>--- a/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h</span><br><span>@@ -19,7 +19,7 @@</span><br><span> #define MSR_IA32_PLATFORM_ID 0x17</span><br><span> #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span style="color: hsl(120, 100%, 40%);">+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_POWER_MISC 0x120</span><br><span> #define MSR_IA32_PERF_CTL 0x199</span><br><span> #define MSR_IA32_MISC_ENABLES 0x1a0</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28871">change 28871</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28871"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f </div>
<div style="display:none"> Gerrit-Change-Number: 28871 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>