[coreboot-gerrit] Change in coreboot[master]: src: Fix IA32_{MPERF, APERF, PM_ENABLE, {HWP_{CAPABILITIES, REQUEST, STATU...
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Mon Oct 1 13:41:54 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28859
Change subject: src: Fix IA32_{MPERF,APERF,PM_ENABLE,{HWP_{CAPABILITIES,REQUEST,STATUS}} names
......................................................................
src: Fix IA32_{MPERF,APERF,PM_ENABLE,{HWP_{CAPABILITIES,REQUEST,STATUS}} names
Change-Id: Ifa1c72fefc7b4c4ddf463cc93643e53ef7c542f3
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/intel/common/common_init.c
M src/include/cpu/x86/msr.h
2 files changed, 12 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/28859/1
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index 98b7f58..d967822 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -104,7 +104,7 @@
config->version = version;
- msr.addrl = MSR_IA32_HWP_CAPABILITIES;
+ msr.addrl = IA32_HWP_CAPABILITIES;
/*
* Highest Performance:
@@ -140,7 +140,7 @@
msr.bit_offset = 8;
config->regs[CPPC_GUARANTEED_PERF] = msr;
- msr.addrl = MSR_IA32_HWP_REQUEST;
+ msr.addrl = IA32_HWP_REQUEST;
/*
* Desired Performance Register:
@@ -181,7 +181,7 @@
*/
config->regs[CPPC_COUNTER_WRAP] = unsupported;
- msr.addrl = MSR_IA32_MPERF;
+ msr.addrl = IA32_MPERF;
/*
* Reference Performance Counter Register:
@@ -191,7 +191,7 @@
msr.bit_offset = 0;
config->regs[CPPC_REF_PERF_COUNTER] = msr;
- msr.addrl = MSR_IA32_APERF;
+ msr.addrl = IA32_APERF;
/*
* Delivered Performance Counter Register:
@@ -199,7 +199,7 @@
*/
config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;
- msr.addrl = MSR_IA32_HWP_STATUS;
+ msr.addrl = IA32_HWP_STATUS;
/*
* Performance Limited Register:
@@ -209,7 +209,7 @@
msr.bit_offset = 2;
config->regs[CPPC_PERF_LIMITED] = msr;
- msr.addrl = MSR_IA32_PM_ENABLE;
+ msr.addrl = IA32_PM_ENABLE;
/*
* CPPC Enable Register:
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index d603421..3bc8584 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -32,8 +32,8 @@
#define MSR_IA32_PAT 0x277
#define IA32_BIOS_UPDT_TRIG 0x79
#define IA32_BIOS_SIGN_ID 0x8b
-#define MSR_IA32_MPERF 0xe7
-#define MSR_IA32_APERF 0xe8
+#define IA32_MPERF 0xe7
+#define IA32_APERF 0xe8
#define IA32_MCG_CAP 0x179
#define IA32_ENERGY_PERF_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
@@ -41,10 +41,10 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401
-#define MSR_IA32_PM_ENABLE 0x770
-#define MSR_IA32_HWP_CAPABILITIES 0x771
-#define MSR_IA32_HWP_REQUEST 0x774
-#define MSR_IA32_HWP_STATUS 0x777
+#define IA32_PM_ENABLE 0x770
+#define IA32_HWP_CAPABILITIES 0x771
+#define IA32_HWP_REQUEST 0x774
+#define IA32_HWP_STATUS 0x777
#define IA32_PQR_ASSOC 0xc8f
/* MSR bits 33:32 encode slot number 0-3 */
#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifa1c72fefc7b4c4ddf463cc93643e53ef7c542f3
Gerrit-Change-Number: 28859
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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