<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28859">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Fix IA32_{MPERF,APERF,PM_ENABLE,{HWP_{CAPABILITIES,REQUEST,STATUS}} names<br><br>Change-Id: Ifa1c72fefc7b4c4ddf463cc93643e53ef7c542f3<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/common/common_init.c<br>M src/include/cpu/x86/msr.h<br>2 files changed, 12 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/28859/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c</span><br><span>index 98b7f58..d967822 100644</span><br><span>--- a/src/cpu/intel/common/common_init.c</span><br><span>+++ b/src/cpu/intel/common/common_init.c</span><br><span>@@ -104,7 +104,7 @@</span><br><span> </span><br><span> config->version = version;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_HWP_CAPABILITIES;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_HWP_CAPABILITIES;</span><br><span> </span><br><span> /*</span><br><span> * Highest Performance:</span><br><span>@@ -140,7 +140,7 @@</span><br><span> msr.bit_offset = 8;</span><br><span> config->regs[CPPC_GUARANTEED_PERF] = msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_HWP_REQUEST;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_HWP_REQUEST;</span><br><span> </span><br><span> /*</span><br><span> * Desired Performance Register:</span><br><span>@@ -181,7 +181,7 @@</span><br><span> */</span><br><span> config->regs[CPPC_COUNTER_WRAP] = unsupported;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_MPERF;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_MPERF;</span><br><span> </span><br><span> /*</span><br><span> * Reference Performance Counter Register:</span><br><span>@@ -191,7 +191,7 @@</span><br><span> msr.bit_offset = 0;</span><br><span> config->regs[CPPC_REF_PERF_COUNTER] = msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_APERF;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_APERF;</span><br><span> </span><br><span> /*</span><br><span> * Delivered Performance Counter Register:</span><br><span>@@ -199,7 +199,7 @@</span><br><span> */</span><br><span> config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_HWP_STATUS;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_HWP_STATUS;</span><br><span> </span><br><span> /*</span><br><span> * Performance Limited Register:</span><br><span>@@ -209,7 +209,7 @@</span><br><span> msr.bit_offset = 2;</span><br><span> config->regs[CPPC_PERF_LIMITED] = msr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- msr.addrl = MSR_IA32_PM_ENABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.addrl = IA32_PM_ENABLE;</span><br><span> </span><br><span> /*</span><br><span> * CPPC Enable Register:</span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index d603421..3bc8584 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -32,8 +32,8 @@</span><br><span> #define MSR_IA32_PAT 0x277</span><br><span> #define IA32_BIOS_UPDT_TRIG 0x79</span><br><span> #define IA32_BIOS_SIGN_ID 0x8b</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_MPERF 0xe7</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_APERF 0xe8</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MPERF 0xe7</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_APERF 0xe8</span><br><span> #define IA32_MCG_CAP 0x179</span><br><span> #define IA32_ENERGY_PERF_BIAS 0x1b0</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span>@@ -41,10 +41,10 @@</span><br><span> #define ENERGY_POLICY_POWERSAVE 15</span><br><span> #define IA32_MC0_CTL 0x400</span><br><span> #define IA32_MC0_STATUS 0x401</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_PM_ENABLE 0x770</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_HWP_CAPABILITIES 0x771</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_HWP_REQUEST 0x774</span><br><span style="color: hsl(0, 100%, 40%);">-#define MSR_IA32_HWP_STATUS 0x777</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_PM_ENABLE 0x770</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_HWP_CAPABILITIES 0x771</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_HWP_REQUEST 0x774</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_HWP_STATUS 0x777</span><br><span> #define IA32_PQR_ASSOC 0xc8f</span><br><span> /* MSR bits 33:32 encode slot number 0-3 */</span><br><span> #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28859">change 28859</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifa1c72fefc7b4c4ddf463cc93643e53ef7c542f3 </div>
<div style="display:none"> Gerrit-Change-Number: 28859 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>