[coreboot-gerrit] Change in coreboot[master]: src: Move IA32_MC0_{CTL, STATUS} to x86/msr.h
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Mon Oct 1 13:41:53 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28858
Change subject: src: Move IA32_MC0_{CTL,STATUS} to x86/msr.h
......................................................................
src: Move IA32_MC0_{CTL,STATUS} to x86/msr.h
Change-Id: I280ea116f3fe443f8b3f570e776ae2a6726728c4
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/intel/fsp_model_206ax/model_206ax.h
M src/cpu/intel/fsp_model_406dx/model_406dx.h
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/model_2065x/model_2065x.h
M src/cpu/intel/model_206ax/model_206ax.h
M src/include/cpu/x86/msr.h
M src/soc/intel/broadwell/include/soc/msr.h
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/denverton_ns/include/soc/msr.h
M src/soc/intel/fsp_broadwell_de/include/soc/msr.h
10 files changed, 2 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28858/1
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h
index 470c6ba..f45081e 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h
@@ -27,7 +27,6 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h
index c23a87e..b5547d0 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h
@@ -28,7 +28,6 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
#define MSR_NO_EVICT_MODE 0x2e0
#define MSR_PIC_MSG_CONTROL 0x2e
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index b718616..fef3e1b 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -42,7 +42,6 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index c4ca738..9b7c876 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -28,7 +28,6 @@
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_FERR_CAPABILITY 0x1f1
#define FERR_ENABLE (1 << 0)
-#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 0ad2329..5c90133 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -27,7 +27,6 @@
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_LT_LOCK_MEMORY 0x2e7
-#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 77b6b4b..efe61a0 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -39,6 +39,8 @@
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
+#define IA32_MC0_CTL 0x400
+#define IA32_MC0_STATUS 0x401
#define MSR_IA32_PM_ENABLE 0x770
#define MSR_IA32_HWP_CAPABILITIES 0x771
#define MSR_IA32_HWP_REQUEST 0x774
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index 0bdf29e..d6f21ea 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -40,7 +40,6 @@
#define MSR_LT_LOCK_MEMORY 0x2e7
#define UNCORE_EMRRphysBase_MSR 0x2f4
#define UNCORE_EMRRphysMask_MSR 0x2f5
-#define IA32_MC0_STATUS 0x401
#define SMM_FEATURE_CONTROL_MSR 0x4e0
#define SMM_CPU_SAVE_EN (1 << 1)
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 0ceef9a..ec7b990 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -64,8 +64,6 @@
#define MSR_EVICT_CTL 0x2e0
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301
-#define IA32_MC0_CTL 0x400
-#define IA32_MC0_STATUS 0x401
#define SMM_FEATURE_CONTROL_MSR 0x4e0
#define SMM_CPU_SAVE_EN (1 << 1)
#define MSR_PKG_POWER_SKU_UNIT 0x606
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h
index 73c5675..962049f 100644
--- a/src/soc/intel/denverton_ns/include/soc/msr.h
+++ b/src/soc/intel/denverton_ns/include/soc/msr.h
@@ -42,7 +42,6 @@
#define MSR_LT_LOCK_MEMORY 0x2e7
#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4
#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5
-#define IA32_MC0_STATUS 0x401
#define SMM_FEATURE_CONTROL_MSR 0x4e0
#define SMM_CPU_SAVE_EN (1 << 1)
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index f240722..ed42fdf 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -21,8 +21,6 @@
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
#define MSR_TURBO_RATIO_LIMIT 0x1ad
-#define IA32_MC0_CTL 0x400
-#define IA32_MC0_STATUS 0x401
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
#define MSR_CONFIG_TDP_NOMINAL 0x648
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I280ea116f3fe443f8b3f570e776ae2a6726728c4
Gerrit-Change-Number: 28858
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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