<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28858">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src: Move IA32_MC0_{CTL,STATUS} to x86/msr.h<br><br>Change-Id: I280ea116f3fe443f8b3f570e776ae2a6726728c4<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/intel/fsp_model_206ax/model_206ax.h<br>M src/cpu/intel/fsp_model_406dx/model_406dx.h<br>M src/cpu/intel/haswell/haswell.h<br>M src/cpu/intel/model_2065x/model_2065x.h<br>M src/cpu/intel/model_206ax/model_206ax.h<br>M src/include/cpu/x86/msr.h<br>M src/soc/intel/broadwell/include/soc/msr.h<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>M src/soc/intel/fsp_broadwell_de/include/soc/msr.h<br>10 files changed, 2 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28858/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>index 470c6ba..f45081e 100644</span><br><span>--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span>diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>index c23a87e..b5547d0 100644</span><br><span>--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_NO_EVICT_MODE 0x2e0</span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span>diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h</span><br><span>index b718616..fef3e1b 100644</span><br><span>--- a/src/cpu/intel/haswell/haswell.h</span><br><span>+++ b/src/cpu/intel/haswell/haswell.h</span><br><span>@@ -42,7 +42,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index c4ca738..9b7c876 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define IA32_FERR_CAPABILITY 0x1f1</span><br><span> #define FERR_ENABLE (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span>diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>index 0ad2329..5c90133 100644</span><br><span>--- a/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>+++ b/src/cpu/intel/model_206ax/model_206ax.h</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #define IA32_PLATFORM_DCA_CAP 0x1f8</span><br><span> #define MSR_TEMPERATURE_TARGET 0x1a2</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> </span><br><span> #define MSR_PIC_MSG_CONTROL 0x2e</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span>diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h</span><br><span>index 77b6b4b..efe61a0 100644</span><br><span>--- a/src/include/cpu/x86/msr.h</span><br><span>+++ b/src/include/cpu/x86/msr.h</span><br><span>@@ -39,6 +39,8 @@</span><br><span> #define ENERGY_POLICY_PERFORMANCE 0</span><br><span> #define ENERGY_POLICY_NORMAL 6</span><br><span> #define ENERGY_POLICY_POWERSAVE 15</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MC0_CTL 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MC0_STATUS 0x401</span><br><span> #define MSR_IA32_PM_ENABLE 0x770</span><br><span> #define MSR_IA32_HWP_CAPABILITIES 0x771</span><br><span> #define MSR_IA32_HWP_REQUEST 0x774</span><br><span>diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>index 0bdf29e..d6f21ea 100644</span><br><span>--- a/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/broadwell/include/soc/msr.h</span><br><span>@@ -40,7 +40,6 @@</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define UNCORE_EMRRphysBase_MSR 0x2f4</span><br><span> #define UNCORE_EMRRphysMask_MSR 0x2f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> </span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>index 0ceef9a..ec7b990 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h</span><br><span>@@ -64,8 +64,6 @@</span><br><span> #define MSR_EVICT_CTL 0x2e0</span><br><span> #define MSR_SGX_OWNEREPOCH0 0x300</span><br><span> #define MSR_SGX_OWNEREPOCH1 0x301</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_CTL 0x400</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index 73c5675..962049f 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -42,7 +42,6 @@</span><br><span> #define MSR_LT_LOCK_MEMORY 0x2e7</span><br><span> #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4</span><br><span> #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define SMM_FEATURE_CONTROL_MSR 0x4e0</span><br><span> #define SMM_CPU_SAVE_EN (1 << 1)</span><br><span> </span><br><span>diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>index f240722..ed42fdf 100644</span><br><span>--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h</span><br><span>@@ -21,8 +21,6 @@</span><br><span> #define MSR_CORE_THREAD_COUNT 0x35</span><br><span> #define MSR_PLATFORM_INFO 0xce</span><br><span> #define MSR_TURBO_RATIO_LIMIT 0x1ad</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_CTL 0x400</span><br><span style="color: hsl(0, 100%, 40%);">-#define IA32_MC0_STATUS 0x401</span><br><span> #define MSR_PKG_POWER_SKU_UNIT 0x606</span><br><span> #define MSR_PKG_POWER_LIMIT 0x610</span><br><span> #define MSR_CONFIG_TDP_NOMINAL 0x648</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28858">change 28858</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I280ea116f3fe443f8b3f570e776ae2a6726728c4 </div>
<div style="display:none"> Gerrit-Change-Number: 28858 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>