[coreboot-gerrit] Change in coreboot[master]: arch/x86: Make mb/romstage.c optional

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28849


Change subject: arch/x86: Make mb/romstage.c optional
......................................................................

arch/x86: Make mb/romstage.c optional

currently src/mainboard/*/romstage.c is mandatory for
compiling, this makes having the file present even though
there is nothing to initialize in the romstage on the
mainboard side. for e.g., mainboard/intel/cannonlake_rvp/romstage.c
Eliminate the need to have empty romstage.c files using the
wildcard function.

BUG=None
BRANCH=None
TEST= build cannonlake_rvp after removing the romstage.c file.

Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/arch/x86/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/28849/1

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 3e272dd..7f85b6a 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -224,7 +224,7 @@
 romstage-y += postcar_loader.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 
-romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c
+romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c)
 romstage-libs ?=
 
 $(eval $(call early_x86_assembly_entry_rule,romstage))

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90
Gerrit-Change-Number: 28849
Gerrit-PatchSet: 1
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
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