[coreboot-gerrit] Change in ...coreboot[master]: qcs405: Implement bitbang UART for bootblock

[Name of user not set (Code Review)]

nsekar at codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29956


Change subject: qcs405: Implement bitbang UART for bootblock
......................................................................

qcs405: Implement bitbang UART for bootblock

This patch replaces the UART in the bootblock of QCS405 with a bitbang
implementation. Since QCS405 hardware UART needs a firmware blob loaded
into it before it becomes usable, it is not really suited for use in the
bootblock (since by the time we can read blobs from SPI, the bootblock
is essentially over anyway). This solution allows us to still have some
console output during early SoC initialization.

Change-Id: Ib631929f6194d0da8571a930230f0eb460fefaa6
Signed-off-by: Sricharan R <sricharan at codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar at codeaurora.org>
---
M src/soc/qualcomm/qcs405/Kconfig
M src/soc/qualcomm/qcs405/Makefile.inc
A src/soc/qualcomm/qcs405/uart_bitbang.c
3 files changed, 47 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29956/1

diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig
index 83c3996..492e80e 100644
--- a/src/soc/qualcomm/qcs405/Kconfig
+++ b/src/soc/qualcomm/qcs405/Kconfig
@@ -11,6 +11,7 @@
 	select GENERIC_UDELAY
 	select HAVE_MONOTONIC_TIMER
 	select ARM64_USE_ARCH_TIMER
+	select HAVE_UART_SPECIAL
 
 if SOC_QUALCOMM_QCS405
 
diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc
index 131f204..f05c987 100644
--- a/src/soc/qualcomm/qcs405/Makefile.inc
+++ b/src/soc/qualcomm/qcs405/Makefile.inc
@@ -7,6 +7,7 @@
 bootblock-y += mmu.c
 bootblock-y += timer.c
 bootblock-y += gpio.c
+bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
 
 ################################################################################
 verstage-y += spi.c
diff --git a/src/soc/qualcomm/qcs405/uart_bitbang.c b/src/soc/qualcomm/qcs405/uart_bitbang.c
new file mode 100644
index 0000000..8827bc4
--- /dev/null
+++ b/src/soc/qualcomm/qcs405/uart_bitbang.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+#include <gpio.h>
+#include <types.h>
+
+#define UART_TX_PIN GPIO(17)
+
+static void set_tx(int line_state)
+{
+	gpio_set(UART_TX_PIN, line_state);
+}
+
+void uart_init(int idx)
+{
+	gpio_output(UART_TX_PIN, 1);
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+	uart_bitbang_tx_byte(data, set_tx);
+}
+
+void uart_tx_flush(int idx)
+{
+	/* unnecessary, PIO Tx means transaction is over when tx_byte returns */
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+	return 0;	/* not implemented */
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib631929f6194d0da8571a930230f0eb460fefaa6
Gerrit-Change-Number: 29956
Gerrit-PatchSet: 1
Gerrit-Owner: nsekar at codeaurora.org
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: nsekar at codeaurora.org
Gerrit-MessageType: newchange
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