[coreboot-gerrit] Change in ...coreboot[master]: qcs405: Add DRAM resources

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nsekar at codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29954


Change subject: qcs405: Add DRAM resources
......................................................................

qcs405: Add DRAM resources

TEST=build

Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185
Signed-off-by: Sricharan R <sricharan at codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar at codeaurora.org>
---
M src/soc/qualcomm/qcs405/include/soc/memlayout.ld
M src/soc/qualcomm/qcs405/include/soc/mmu.h
M src/soc/qualcomm/qcs405/include/soc/symbols.h
M src/soc/qualcomm/qcs405/soc.c
4 files changed, 17 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29954/1

diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
index c0f5759..03c6edb 100644
--- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld
@@ -45,7 +45,9 @@
 	REGION(pmic, 0x8D8F000, 0xA000, 4096)*/
 	BSRAM_END(0x8D80000)
 
-	DRAM_START(0x90000000)
-	POSTRAM_CBFS_CACHE(0x90000000, 384K)
-	RAMSTAGE(0x90800000, 128K)
+	DRAM_START(0x80000000)
+	/* Various hardware/software subsystems make use of this area */
+	REGION(dram_reserved, 0x85000000, 0x1A800000, 4096)
+	POSTRAM_CBFS_CACHE(0x9F800000, 384K)
+	RAMSTAGE(0x9F860000, 128K)
 }
diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h
index bc42e72..75cb320 100644
--- a/src/soc/qualcomm/qcs405/include/soc/mmu.h
+++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h
@@ -16,6 +16,8 @@
 #ifndef _SOC_QUALCOMM_QCS405_MMU_H__
 #define _SOC_QUALCOMM_QCS405_MMU_H__
 
+#define DRAMSIZE4GB 0x100000000
+
 void qcs405_mmu_init(void);
 
 #endif  // _SOC_QUALCOMM_QCS405_MMU_H_
diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h
index 7b35c55..f7cdc8d 100644
--- a/src/soc/qualcomm/qcs405/include/soc/symbols.h
+++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h
@@ -26,4 +26,8 @@
 extern u8 _ebsram[];
 #define _bsram_size (_ebsram - _bsram)
 
+extern u8 _dram_reserved[];
+extern u8 _edram_reserved[];
+#define _dram_reserved_size (_edram_reserved - _dram_reserved)
+
 #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_
diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c
index 7870219..c97822a 100644
--- a/src/soc/qualcomm/qcs405/soc.c
+++ b/src/soc/qualcomm/qcs405/soc.c
@@ -13,12 +13,17 @@
  * GNU General Public License for more details.
  */
 
+#include <symbols.h>
 #include <device/device.h>
 #include <timestamp.h>
+#include <soc/mmu.h>
+#include <soc/symbols.h>
 
 static void soc_read_resources(device_t dev)
 {
-
+	ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB);
+	reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB,
+				_dram_reserved_size / KiB);
 }
 
 static void soc_init(device_t dev)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185
Gerrit-Change-Number: 29954
Gerrit-PatchSet: 1
Gerrit-Owner: nsekar at codeaurora.org
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: nsekar at codeaurora.org
Gerrit-MessageType: newchange
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