[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/apl: Disable LPC Clock Run feature after FSP-S

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29900


Change subject: soc/intel/apl: Disable LPC Clock Run feature after FSP-S
......................................................................

soc/intel/apl: Disable LPC Clock Run feature after FSP-S

The EDS clearly says that it shouldn't be enabled before all LPC devices
are initialized.

Change-Id: Ibfad2555cc78ed9639f4f8b54d4b5b4ad28db65d
Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
M src/soc/intel/apollolake/chip.c
1 file changed, 8 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/29900/1

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 85fe30c..cbd5aba 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -35,6 +35,7 @@
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/pmclib.h>
 #include <romstage_handoff.h>
 #include <soc/cpu.h>
@@ -657,6 +658,13 @@
 	silconfig->UsbOtg = dev->enabled;
 }
 
+void soc_fsp_silicon_init_fixups(void)
+{
+	/* FSP-S enables LPC Clock Run even though it should only
+	   happen after all LPC devices are fully initialized. */
+	lpc_disable_pci_clkrun();
+}
+
 struct chip_operations soc_intel_apollolake_ops = {
 	CHIP_NAME("Intel Apollolake SOC")
 	.enable_dev = &enable_dev,

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibfad2555cc78ed9639f4f8b54d4b5b4ad28db65d
Gerrit-Change-Number: 29900
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Nico Huber <nico.h at gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-MessageType: newchange
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