[coreboot-gerrit] Change in ...coreboot[master]: {mb, nb, soc/fsp_baytrail}: Get rid of dump_mem()
HAOUAS Elyes (Code Review)
gerrit at coreboot.org
Tue Nov 27 09:35:19 CET 2018
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29853
Change subject: {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()
......................................................................
{mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()
Use hexdump() instead of dump_mem().
Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/amd/mahogany_fam10/romstage.c
M src/mainboard/asus/m4a78-em/romstage.c
M src/mainboard/asus/m4a785-m/romstage.c
M src/mainboard/asus/m5a88-v/romstage.c
M src/mainboard/gigabyte/ma785gm/romstage.c
M src/mainboard/gigabyte/ma785gmt/romstage.c
M src/mainboard/iei/kino-780am2-fam10/romstage.c
M src/mainboard/jetway/pa78vm5/romstage.c
M src/mainboard/supermicro/h8scm_fam10/romstage.c
M src/northbridge/amd/amdfam10/debug.c
M src/northbridge/amd/amdfam10/debug.h
M src/northbridge/intel/e7505/debug.c
M src/northbridge/intel/e7505/debug.h
M src/northbridge/intel/fsp_rangeley/northbridge.h
M src/northbridge/intel/haswell/haswell.h
M src/northbridge/intel/i945/debug.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/nehalem/nehalem.h
M src/northbridge/intel/sandybridge/sandybridge.h
M src/soc/intel/fsp_baytrail/include/soc/baytrail.h
20 files changed, 0 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29853/1
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 39ff7a0..180fa5d 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -102,8 +102,6 @@
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 96d80cc..4860787 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -102,8 +102,6 @@
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 8eb9226..f8e2e32 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -103,8 +103,6 @@
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index bb43dd5..9eec8c0 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -106,8 +106,6 @@
console_init();
printk(BIOS_DEBUG, "\n");
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 098baac..9255b01 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -98,8 +98,6 @@
it8718f_disable_reboot(GPIO_DEV);
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 05d2e04..cd7ff1e 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -98,8 +98,6 @@
it8718f_disable_reboot(GPIO_DEV);
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index fc1b32f..46da224 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -100,8 +100,6 @@
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index f75c5a4..f738341 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -105,8 +105,6 @@
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 3eeaeda..62f5f8d 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -112,8 +112,6 @@
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 067c299..55a00e1 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -299,19 +299,6 @@
}
}
-void dump_mem(u32 start, u32 end)
-{
- u32 i;
- printk(BIOS_DEBUG, "dump_mem:");
- for (i = start; i < end; i++) {
- if ((i & 0xf) == 0) {
- printk(BIOS_DEBUG, "\n%08x:", i);
- }
- printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
- }
- printk(BIOS_DEBUG, "\n");
-}
-
#if IS_ENABLED(CONFIG_DIMM_DDR2)
void print_tx(const char *strval, u32 val)
{
diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h
index a4ecfe9..a23303e 100644
--- a/src/northbridge/amd/amdfam10/debug.h
+++ b/src/northbridge/amd/amdfam10/debug.h
@@ -38,7 +38,6 @@
#endif
void dump_io_resources(u32 port);
-void dump_mem(u32 start, u32 end);
void print_tx(const char *strval, u32 val);
void print_t(const char *strval);
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index f3a27e2..c21e321 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -183,15 +183,3 @@
port++;
}
}
-
-void dump_mem(unsigned start, unsigned end)
-{
- unsigned i;
- printk(BIOS_DEBUG, "dump_mem:");
- for (i = start; i < end; i++) {
- if ((i & 0xf)==0)
- printk(BIOS_DEBUG, "\n%08x:", i);
- printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
- }
- printk(BIOS_DEBUG, "\n");
-}
diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h
index 238c500..98ca848 100644
--- a/src/northbridge/intel/e7505/debug.h
+++ b/src/northbridge/intel/e7505/debug.h
@@ -22,6 +22,5 @@
void dump_spd_registers(const struct mem_controller *ctrl);
void dump_smbus_registers(void);
void dump_io_resources(unsigned port);
-void dump_mem(unsigned start, unsigned end);
#endif
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h
index f68d175..11089a5 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.h
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.h
@@ -69,7 +69,6 @@
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
-void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#ifndef __SIMPLE_DEVICE__
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 33818ee..574a7f8 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -222,7 +222,6 @@
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
-void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index ef4f17b..c52f2a6 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -96,15 +96,3 @@
printk(BIOS_DEBUG, "\n");
}
}
-
-void dump_mem(unsigned int start, unsigned int end)
-{
- unsigned int i;
- printk(BIOS_DEBUG, "dump_mem:");
- for (i = start; i < end; i++) {
- if ((i & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%08x:", i);
- printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
- }
- printk(BIOS_DEBUG, "\n");
-}
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 65a40e7..757eb52 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -379,7 +379,6 @@
void dump_pci_device(unsigned int dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
-void dump_mem(unsigned int start, unsigned int end);
u32 decode_igd_memory_size(u32 gms);
u32 decode_tseg_size(const u8 esmramc);
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 5756c90..b0e8490 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -277,7 +277,6 @@
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
-void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* !__SMM__ */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index faa9cd90..9e3da4b 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -219,7 +219,6 @@
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
-void dump_mem(unsigned start, unsigned end);
#endif /* !__SMM__ */
diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
index 82fd0a1..68bdd12 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
@@ -63,7 +63,6 @@
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_spd_registers(void);
-void dump_mem(unsigned start, unsigned end);
void report_platform_info(void);
#endif /* __PRE_RAM__ */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f
Gerrit-Change-Number: 29853
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes <ehaouas at noos.fr>
Gerrit-MessageType: newchange
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