[coreboot-gerrit] Change in ...coreboot[master]: Documentation/../../icelake: Add Ice Lake coreboot development docume...

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29805


Change subject: Documentation/../../icelake: Add Ice Lake coreboot development documentation
......................................................................

Documentation/../../icelake: Add Ice Lake coreboot development documentation

Add documentation for Ice Lake processor family coreboot development.

Documented so far:
* What is Ice Lake
* Development Strategy
* Create coreboot Image
* Flashing coreboot

Change-Id: Ief4df6ca11f95b75ecddeb560f7887bfadced086
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
A Documentation/soc/intel/icelake/IceLake_Coreboot_Development.md
M Documentation/soc/intel/icelake/index.md
2 files changed, 60 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29805/1

diff --git a/Documentation/soc/intel/icelake/IceLake_Coreboot_Development.md b/Documentation/soc/intel/icelake/IceLake_Coreboot_Development.md
new file mode 100644
index 0000000..d60cf79
--- /dev/null
+++ b/Documentation/soc/intel/icelake/IceLake_Coreboot_Development.md
@@ -0,0 +1,56 @@
+# Intel Ice Lake coreboot development
+
+## Introduction
+
+This document captures the coreboot development strategy for Intel SoC named Ice lake.
+
+The Ice Lake processor family is the next generation Intel® Core processor family.
+These processors utilize Intels industry-leading 10 nm+ process technology.
+
+* Reference: https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html
+
+## Development Strategy
+
+Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model".
+
+1. Intel develops initial Firmware code for Ice Lake SoC.
+   * CL: https://review.coreboot.org/#/c/coreboot/+/29162/
+
+2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC.
+   * CL: https://review.coreboot.org/#/c/coreboot/+/29164/
+
+3. OEMs to design based on reference platform and make use of mainboard sample code. Rigth now Dragonegg is one of Ice Lake based mainboard developed by Google
+   * CL: https://review.coreboot.org/#/c/coreboot/+/29749/
+
+### Summary:
+* SoC as Ice Lake.
+* Reference platform as icelake_rvp.
+* OEM board as Dragonegg.
+
+## Create coreboot Image
+
+1. Clone latest coreboot code as below
+$ git clone http://review.coreboot.org/p/coreboot
+
+2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations
+
+Note:
+Consider the fact that ucode an ME binary release process will remain same for Ice Lake program as well.
+After PRQ,FSP binary will be available externally as any other program.
+
+3. Create coreboot .config
+
+4. Build toolchain
+
+CPUS=$(nproc--ignore=1)  make  crossgcc-i386  iasl
+
+5. Build image
+$ make # the image is generated as build/coreboot.rom
+
+## Flashing coreboot
+
+Flashing is the same as other Intel boards:
+
+$ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on
+$ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image>
+$ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off
diff --git a/Documentation/soc/intel/icelake/index.md b/Documentation/soc/intel/icelake/index.md
index b4f512c..c295f8a 100644
--- a/Documentation/soc/intel/icelake/index.md
+++ b/Documentation/soc/intel/icelake/index.md
@@ -2,6 +2,10 @@
 
 This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs.
 
+## Ice Lake coreboot development
+
+- [Ice Lake coreboot development](IceLake_Coreboot_Development.md)
+
 ## Multiprocessor Init
 
 - [Multiprocessor Init](MultiProcessorInit.md)

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ief4df6ca11f95b75ecddeb560f7887bfadced086
Gerrit-Change-Number: 29805
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-MessageType: newchange
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