[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Enable DPTF
Duncan Laurie (Code Review)
gerrit at coreboot.org
Wed Nov 21 02:45:58 CET 2018
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29762
Change subject: mb/google/sarien: Enable DPTF
......................................................................
mb/google/sarien: Enable DPTF
Enable DPTF support for sarien/arcada boards. This is currently
using placeholder values that are identical that will be updated
after thermal tuning is done.
Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5
Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
M src/mainboard/google/sarien/dsdt.asl
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
5 files changed, 131 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29762/1
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index 110a214..e544ed6 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -63,4 +63,15 @@
#include <ec/google/wilco/acpi/ec.asl>
}
#endif
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ /* Per board variant specific definitions. */
+ #include <variant/acpi/dptf.asl>
+ /* Include soc specific DPTF changes */
+ #include <soc/intel/cannonlake/acpi/dptf.asl>
+ /* Include common dptf ASL files */
+ #include <soc/intel/common/acpi/dptf/dptf.asl>
+ }
}
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index ee1cca0..4bd2d90 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -30,6 +30,7 @@
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
+ register "dptf_enable" = "1"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..2d35878
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 100
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "Thermal 1"
+#define DPTF_TSR0_PASSIVE 55
+#define DPTF_TSR0_CRITICAL 80
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "Thermal 2"
+#define DPTF_TSR1_PASSIVE 55
+#define DPTF_TSR1_CRITICAL 80
+
+#undef DPTF_ENABLE_FAN_CONTROL
+#undef DPTF_ENABLE_CHARGER
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
+
+ /* CPU Effect on Board */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 32000, /* TimeWindowMaximum */
+ 100 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 15000, /* PowerLimitMinimum */
+ 44000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 32000, /* TimeWindowMaximum */
+ 100 /* StepSize */
+ }
+})
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index b33c923..66f1711 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -30,6 +30,7 @@
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"
+ register "dptf_enable" = "1"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..2d35878
--- /dev/null
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 100
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "Thermal 1"
+#define DPTF_TSR0_PASSIVE 55
+#define DPTF_TSR0_CRITICAL 80
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "Thermal 2"
+#define DPTF_TSR1_PASSIVE 55
+#define DPTF_TSR1_CRITICAL 80
+
+#undef DPTF_ENABLE_FAN_CONTROL
+#undef DPTF_ENABLE_CHARGER
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
+
+ /* CPU Effect on Board */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 32000, /* TimeWindowMaximum */
+ 100 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 15000, /* PowerLimitMinimum */
+ 44000, /* PowerLimitMaximum */
+ 28000, /* TimeWindowMinimum */
+ 32000, /* TimeWindowMaximum */
+ 100 /* StepSize */
+ }
+})
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5
Gerrit-Change-Number: 29762
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
Gerrit-MessageType: newchange
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