[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: add vmx support via CPU_INTEL_COMMON

Matt DeVillier (Code Review) gerrit at coreboot.org
Sun Nov 11 00:54:11 CET 2018


Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/29570


Change subject: soc/intel/braswell: add vmx support via CPU_INTEL_COMMON
......................................................................

soc/intel/braswell: add vmx support via CPU_INTEL_COMMON

Braswell allready supported vmx, but offered no mechanism to unset it, nor
to set the lock bit required for Windows to recognize virtualization.
Enable this functionality by adding CPU_INTEL_COMMON config.

Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows
virtualization as enabled.

Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/Makefile.inc
M src/soc/intel/braswell/cpu.c
3 files changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29570/1

diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 2ba7992..50c2802 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -47,6 +47,7 @@
 	select GENERIC_GPIO_LIB
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_SWSMISCI
+	select CPU_INTEL_COMMON
 
 config VBOOT
 	select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 38dcf5a..ac1bacd 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -7,6 +7,7 @@
 subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../cpu/intel/common
 
 romstage-y += gpio_support.c
 romstage-y += iosf.c
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 195dba4..9063c2a 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -16,6 +16,7 @@
 
 #include <console/console.h>
 #include <cpu/cpu.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/turbo.h>
 #include <cpu/x86/cache.h>
@@ -60,6 +61,9 @@
 	if (lapicid())
 		enable_turbo();
 
+	/* Set virtualization based on Kconfig option */
+	set_vmx();
+
 	/* Set core MSRs */
 	reg_script_run(core_msr_script);
 

-- 
To view, visit https://review.coreboot.org/29570
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992
Gerrit-Change-Number: 29570
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181110/367d06f6/attachment.html>


More information about the coreboot-gerrit mailing list