[coreboot-gerrit] Change in coreboot[master]: mb/google/sarien: Set runtime IRQs to reset on PLTRST
Duncan Laurie (Code Review)
gerrit at coreboot.org
Thu Nov 8 19:49:54 CET 2018
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/29539 )
Change subject: mb/google/sarien: Set runtime IRQs to reset on PLTRST
......................................................................
mb/google/sarien: Set runtime IRQs to reset on PLTRST
GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ strom after S3 resume.
For sarien/arcada these are all runtime IRQs only, not wake capable.
Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f
Signed-off-by: Duncan Laurie <dlaurie at google.com>
Reviewed-on: https://review.coreboot.org/29539
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Furquan Shaikh <furquan at google.com>
---
M src/mainboard/google/sarien/variants/arcada/gpio.c
M src/mainboard/google/sarien/variants/sarien/gpio.c
2 files changed, 12 insertions(+), 12 deletions(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index eb4ee76..91ff089 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -46,7 +46,7 @@
/* CORE_VID0 */
/* CORE_VID1 */
/* VRALERT# */ PAD_NC(GPP_B2, NONE),
-/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP,
+/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
@@ -93,10 +93,10 @@
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
-/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP,
+/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TS_INT# */
-/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP,
+/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),
/* SPI1_MISO */ PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */
@@ -117,7 +117,7 @@
/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
-/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),
/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),
@@ -232,7 +232,7 @@
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
-/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 690af1f..31b42ef 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -46,7 +46,7 @@
/* CORE_VID0 */
/* CORE_VID1 */
/* VRALERT# */ PAD_NC(GPP_B2, NONE),
-/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP,
+/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
@@ -63,7 +63,7 @@
/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
-/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, DEEP,
+/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* HDD_FALL_INT */
/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
@@ -94,10 +94,10 @@
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),
-/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP,
+/* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TS_INT# */
-/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, DEEP,
+/* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),
/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),
@@ -116,7 +116,7 @@
/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
-/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE),
/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE),
@@ -143,7 +143,7 @@
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
-/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, DEEP,
+/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* FFS_INT2 */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
@@ -232,7 +232,7 @@
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
/* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
/* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
-/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
+/* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
--
To view, visit https://review.coreboot.org/29539
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f
Gerrit-Change-Number: 29539
Gerrit-PatchSet: 3
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181108/919373c1/attachment.html>
More information about the coreboot-gerrit
mailing list