[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl3: Disable CLKREQ of PCIe root ports
Mario Scheithauer (Code Review)
gerrit at coreboot.org
Tue Nov 6 10:38:26 CET 2018
Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29502
Change subject: siemens/mc_apl3: Disable CLKREQ of PCIe root ports
......................................................................
siemens/mc_apl3: Disable CLKREQ of PCIe root ports
All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefor the ports are marked with "CLKREQ_DISABLED".
Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29502/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index f3e8a77..13ac4b5 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -7,10 +7,10 @@
register "sci_irq" = "SCIS_IRQ10"
# Disable unused clkreq of PCIe root ports
- register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
- register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
- register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
- register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
+ register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
+ register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4
Gerrit-Change-Number: 29502
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
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