<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29502">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">siemens/mc_apl3: Disable CLKREQ of PCIe root ports<br><br>All PCIe root ports of this mainboard do not have an associated CLKREQ<br>signal. Therefor the ports are marked with "CLKREQ_DISABLED".<br><br>Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb<br>1 file changed, 4 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29502/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb</span><br><span>index f3e8a77..13ac4b5 100644</span><br><span>--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb</span><br><span>+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb</span><br><span>@@ -7,10 +7,10 @@</span><br><span>       register "sci_irq" = "SCIS_IRQ10"</span><br><span> </span><br><span>    # Disable unused clkreq of PCIe root ports</span><br><span style="color: hsl(0, 100%, 40%);">-      register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge</span><br><span style="color: hsl(0, 100%, 40%);">-    register "pcie_rp_clkreq_pin[1]" = "2" # FPGA</span><br><span style="color: hsl(0, 100%, 40%);">-       register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY</span><br><span style="color: hsl(0, 100%, 40%);">-     register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY</span><br><span style="color: hsl(120, 100%, 40%);">+   register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+      register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+      register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"</span><br><span style="color: hsl(120, 100%, 40%);">+      register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"</span><br><span>     register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"</span><br><span>     register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29502">change 29502</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29502"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4 </div>
<div style="display:none"> Gerrit-Change-Number: 29502 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>