[coreboot-gerrit] Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/29469

to review the following change.


Change subject: mb/google/kahlee: edp panel initialization time tuning
......................................................................

mb/google/kahlee: edp panel initialization time tuning

1.adding two parameters for panel initialization timing.
  > lvds_poseq_varybl_to_blon
  > lvds_poseq_blon_to_varybl
2.changing GPIO EP133 to high as default.

BUG=b:118011567
TEST=emerge-grunt coreboot

Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb
Signed-off-by: Chris Wang <chris.wang at amd.corp-partner.google.com>
---
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
M src/mainboard/google/kahlee/variants/liara/devicetree.cb
M src/soc/amd/stoneyridge/chip.h
4 files changed, 20 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29469/1

diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index a0bd8cd..e1275f0 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -16,6 +16,8 @@
 #include <chip.h>
 #include <amdblocks/agesawrapper.h>
 #include <boardid.h>
+#include <console/console.h>
+#include <soc/pci_devs.h>
 
 #define DIMMS_PER_CHANNEL 1
 #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
@@ -75,5 +77,18 @@
 
 void set_board_env_params(GNB_ENV_CONFIGURATION *params)
 {
+	const struct soc_amd_stoneyridge_config *cfg;
+	const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+	if (!dev || !dev->chip_info) {
+		printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree"
+					" config, \n");
+		return;
+	}
+	cfg = dev->chip_info;
+	if ((cfg->lvds_poseq_blon_to_varybl) && (cfg->lvds_poseq_varybl_to_blon)) {
+		printk(BIOS_DEBUG, "Change panel init timing\n");
+		params->LvdsPowerOnSeqVaryBlToBlon = cfg->lvds_poseq_varybl_to_blon;
+		params->LvdsPowerOnSeqBlonToVaryBl = cfg->lvds_poseq_blon_to_varybl;
+	}
 	params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE;
 }
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 6095a08..5c74c89 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -218,7 +218,7 @@
 	PAD_GPI(GPIO_130, PULL_UP),
 
 	/* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */
-	PAD_GPO(GPIO_133, HIGH),
+	PAD_GPO(GPIO_133, LOW),
 
 	/* GPIO_135 - BCLK Buffer Enable */
 	PAD_GPO(GPIO_135, HIGH),
diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
index 343fbeb..8b964c2 100644
--- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
@@ -20,7 +20,8 @@
 	register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
 	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
 	register "uma_size" = "32 * MiB"
-
+    register "lvds_poseq_varybl_to_blon" = "0x5"
+    register "lvds_poseq_blon_to_varybl" = "0x5"
 	# Enable I2C0 for audio, USB3 hub at 400kHz
 	register "i2c[0]" = "{
 		.speed = I2C_SPEED_FAST,
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 320bef0..29ce026 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -63,6 +63,8 @@
 	u8 stapm_percent;
 	u32 stapm_time_ms;
 	u32 stapm_power_mw;
+	u8 lvds_poseq_varybl_to_blon;
+	u8 lvds_poseq_blon_to_varybl;
 };
 
 typedef struct soc_amd_stoneyridge_config config_t;

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb
Gerrit-Change-Number: 29469
Gerrit-PatchSet: 1
Gerrit-Owner: chris wang <Chris.Wang at amd.com>
Gerrit-Reviewer: Chris Wang <chris.wang at amd.corp-partner.google.com>
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