[coreboot-gerrit] Change in coreboot[master]: mb/google/sarien: Enable WWAN detection

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29430 )

Change subject: mb/google/sarien: Enable WWAN detection
......................................................................

mb/google/sarien: Enable WWAN detection

WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF#
set to high more than 10 ms, so force RESET#(GPP_D21) to low at
bootblock stage to match the sequence.

BUG=N/A
TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB
devices through lsusb.

Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Reviewed-on: https://review.coreboot.org/29430
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/mainboard/google/sarien/variants/arcada/gpio.c
M src/mainboard/google/sarien/variants/sarien/gpio.c
2 files changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved



diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index 86da3ec..eb4ee76 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -234,6 +234,8 @@
 /* I2C4_SCL */		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
 /* DMIC_DATA1 */	PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
 				 EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
+/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
+/* SPI1_IO2 */		PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
 /* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
 /* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 3656afb..690af1f 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -234,6 +234,8 @@
 /* I2C4_SCL */		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
 /* DMIC_DATA1 */	PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP,
 				 EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
+/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
+/* SPI1_IO2 */		PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
 /* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
 /* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133
Gerrit-Change-Number: 29430
Gerrit-PatchSet: 4
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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