[coreboot-gerrit] Change in coreboot[master]: intel/nb/*/gma: Use new common PMBASE API
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Fri Nov 2 18:45:39 CET 2018
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29439
Change subject: intel/nb/*/gma: Use new common PMBASE API
......................................................................
intel/nb/*/gma: Use new common PMBASE API
* Introduce common function to enable TCO SCI.
* Use new PMBASE functions to get rid of get_pmbase
Change-Id: I6b5977b10d1e38b45e09530e9dcabbd5f42facb2
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/fsp_sandybridge/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/southbridge/intel/common/pmutil.c
M src/southbridge/intel/common/pmutil.h
6 files changed, 34 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/29439/1
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c
index cba5869..801fa6f 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.c
+++ b/src/northbridge/intel/fsp_sandybridge/gma.c
@@ -22,6 +22,7 @@
#include <southbridge/intel/fsp_bd82x6x/nvs.h>
#include <drivers/intel/gma/opregion.h>
#include <drivers/intel/gma/intel_bios.h>
+#include <southbridge/intel/common/pmbase.h>
#include <cbmem.h>
@@ -105,17 +106,11 @@
u16 reg16;
/* clear DMISCI status */
- reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
- reg16 &= DMISCI_STS;
- outw(DEFAULT_PMBASE + TCO1_STS, reg16);
+ reg16 = read_pmbase16(TCO1_STS);
+ reg16 &= ~DMISCI_STS;
+ write_pmbase16(TCO1_STS, reg16);
- /* clear acpi tco status */
- outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
-
- /* enable acpi tco scis */
- reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
- reg16 |= TCOSCI_EN;
- outw(DEFAULT_PMBASE + GPE0_EN, reg16);
+ southbridge_enable_tco_sci();
}
static void gma_init(struct device *dev)
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index efc9fa3..2c05d0f 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -27,6 +27,7 @@
#include <cpu/intel/haswell/haswell.h>
#include <drivers/intel/gma/opregion.h>
#include <southbridge/intel/lynxpoint/nvs.h>
+#include <southbridge/intel/common/pmbase.h>
#include <stdlib.h>
#include <string.h>
@@ -444,9 +445,9 @@
u16 reg16;
/* clear DMISCI status */
- reg16 = inw(get_pmbase() + TCO1_STS);
- reg16 &= DMISCI_STS;
- outw(get_pmbase() + TCO1_STS, reg16);
+ reg16 = read_pmbase16(TCO1_STS);
+ reg16 &= ~DMISCI_STS;
+ write_pmbase16(TCO1_STS, reg16);
/* clear and enable ACPI TCO SCI */
enable_tco_sci();
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index b89215d..77467bc 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -30,6 +30,7 @@
#include <pc80/vga_io.h>
#include <southbridge/intel/ibexpeak/nvs.h>
#include <drivers/intel/gma/opregion.h>
+#include <southbridge/intel/common/pmbase.h>
#include <cbmem.h>
#include "chip.h"
@@ -577,17 +578,11 @@
u16 reg16;
/* clear DMISCI status */
- reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
- reg16 &= DMISCI_STS;
- outw(DEFAULT_PMBASE + TCO1_STS, reg16);
+ reg16 = read_pmbase16(TCO1_STS);
+ reg16 &= ~DMISCI_STS;
+ write_pmbase16(TCO1_STS, reg16);
- /* clear acpi tco status */
- outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
-
- /* enable acpi tco scis */
- reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
- reg16 |= TCOSCI_EN;
- outw(DEFAULT_PMBASE + GPE0_EN, reg16);
+ southbridge_enable_tco_sci();
}
static void gma_func0_init(struct device *dev)
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index cd8f7b9..f54beb5 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -25,6 +25,7 @@
#include <drivers/intel/gma/libgfxinit.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <drivers/intel/gma/opregion.h>
+#include <southbridge/intel/common/pmbase.h>
#include <cbmem.h>
#include "chip.h"
@@ -599,17 +600,11 @@
u16 reg16;
/* clear DMISCI status */
- reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
- reg16 &= DMISCI_STS;
- outw(DEFAULT_PMBASE + TCO1_STS, reg16);
+ reg16 = read_pmbase16(TCO1_STS);
+ reg16 &= ~DMISCI_STS;
+ write_pmbase16(TCO1_STS, reg16);
- /* clear acpi tco status */
- outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
-
- /* enable acpi tco scis */
- reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
- reg16 |= TCOSCI_EN;
- outw(DEFAULT_PMBASE + GPE0_EN, reg16);
+ southbridge_enable_tco_sci();
}
static void gma_func0_init(struct device *dev)
diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c
index ac72eba..7d0aec6 100644
--- a/src/southbridge/intel/common/pmutil.c
+++ b/src/southbridge/intel/common/pmutil.c
@@ -197,6 +197,20 @@
printk(BIOS_DEBUG, "\n");
}
+/* Used by Intel GMA */
+void southbridge_enable_tco_sci(void)
+{
+ u16 reg16;
+
+ /* clear acpi tco status */
+ write_pmbase32(GPE0_STS, TCOSCI_STS);
+
+ /* enable acpi tco scis */
+ reg16 = read_pmbase16(GPE0_EN);
+ reg16 |= TCOSCI_EN;
+ write_pmbase16(GPE0_EN, reg16);
+}
+
/**
* @brief Set the EOS bit
*/
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index 26134d9..64a30e4 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -110,6 +110,7 @@
void dump_pm1_status(u16 pm1_sts);
void dump_tco_status(u32 tco_sts);
u32 reset_tco_status(void);
+void southbridge_enable_tco_sci(void);
void dump_gpe0_status(u64 gpe0_sts);
u64 reset_gpe0_status(void);
void dump_smi_status(u32 smi_sts);
--
To view, visit https://review.coreboot.org/29439
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6b5977b10d1e38b45e09530e9dcabbd5f42facb2
Gerrit-Change-Number: 29439
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181102/4d113240/attachment-0001.html>
More information about the coreboot-gerrit
mailing list