[coreboot-gerrit] Change in coreboot[master]: mb/lenovo/x220: Add x1 as a variant
Bill XIE (Code Review)
gerrit at coreboot.org
Fri Nov 2 13:38:39 CET 2018
Bill XIE has uploaded this change for review. ( https://review.coreboot.org/29434
Change subject: mb/lenovo/x220: Add x1 as a variant
......................................................................
mb/lenovo/x220: Add x1 as a variant
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a
clone of X220, with additional USB3 controller on pci-e (as i7 variant
of x220, and a powered ESATA port wired to ata4 (Linux' annotation).
Tested:
- CPU i5-2520M
- Slotted DIMM 8GiB
- Camera
- Mini pci-e on wlan slot
- Msata on wwan slot
- On board SDHCI connected to pci-e
- USB3 controller connected to pci-e
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
SeaBIOS, or Linux payload (Heads)
Not tested:
- Fingerprint reader on USB2
- Onboard USB2 interfaces (wlan slot, wwan slot)
Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1
Signed-off-by: Bill XIE <persmule at gmail.com>
---
M src/mainboard/lenovo/x220/Kconfig
M src/mainboard/lenovo/x220/Kconfig.name
M src/mainboard/lenovo/x220/Makefile.inc
A src/mainboard/lenovo/x220/variants/x1/devicetree.cb
A src/mainboard/lenovo/x220/variants/x1/gpio.c
R src/mainboard/lenovo/x220/variants/x220/devicetree.cb
R src/mainboard/lenovo/x220/variants/x220/gpio.c
7 files changed, 450 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29434/1
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index a710c84..9a18e9b 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -30,9 +30,22 @@
string
default lenovo/x220
+config VARIANT_DIR
+ string
+ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+ default "x1" if BOARD_LENOVO_X1
+
+
config MAINBOARD_PART_NUMBER
string
- default "ThinkPad X220"
+ default "ThinkPad X220" if BOARD_LENOVO_X220
+ default "ThinkPad X220i" if BOARD_LENOVO_X220I
+ default "ThinkPad X1" if BOARD_LENOVO_X1
+
+config DEVICETREE
+ string
+ default "variants/x220/devicetree.cb" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+ default "variants/x1/devicetree.cb" if BOARD_LENOVO_X1
config MAX_CPUS
int
@@ -49,6 +62,7 @@
config VGA_BIOS_FILE
string
default "pci8086,0116.rom" if BOARD_LENOVO_X220I
+ # FIXME: x1 with i3 cpu may also use "pci8086,0116.rom"
default "pci8086,0126.rom"
config VGA_BIOS_ID
@@ -62,6 +76,11 @@
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
- default 0x21db
+ default 0x21db if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+ default 0x21e8 if BOARD_LENOVO_X1
-endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+# Override the default variant behavior, since the data.vbt is the same
+config INTEL_GMA_VBT_FILE
+ default "src/mainboard/$(MAINBOARDDIR)/data.vbt"
+
+endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name
index 0f9d3fc..988ac4f 100644
--- a/src/mainboard/lenovo/x220/Kconfig.name
+++ b/src/mainboard/lenovo/x220/Kconfig.name
@@ -3,3 +3,6 @@
config BOARD_LENOVO_X220I
bool "ThinkPad X220i"
+
+config BOARD_LENOVO_X1
+ bool "ThinkPad X1"
diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc
index 2dab950..ee968e2 100644
--- a/src/mainboard/lenovo/x220/Makefile.inc
+++ b/src/mainboard/lenovo/x220/Makefile.inc
@@ -14,6 +14,6 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += gpio.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x220/variants/x1/devicetree.cb b/src/mainboard/lenovo/x220/variants/x1/devicetree.cb
new file mode 100644
index 0000000..678c6c3
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x1/devicetree.cb
@@ -0,0 +1,203 @@
+chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+
+ register "gpu_dp_b_hotplug" = "0x04"
+ register "gpu_dp_c_hotplug" = "0x04"
+ register "gpu_dp_d_hotplug" = "0x04"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "3"
+ register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms
+ register "gpu_panel_power_down_delay" = "250" # T5+T6: 35ms
+ register "gpu_panel_power_backlight_on_delay" = "2500" # T3: 250ms
+ register "gpu_panel_power_backlight_off_delay" = "2500" # T4: 250ms
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gpu_cpu_backlight" = "0x1312"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ register "pci_mmio_size" = "1024"
+
+ device domain 0 on
+ device pci 00.0 on
+ subsystemid 0x17aa 0x21e8
+ end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on
+ subsystemid 0x17aa 0x21e8
+ end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi1_routing" = "2"
+ register "gpi13_routing" = "2"
+
+ # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap)
+ register "sata_port_map" = "0x1d"
+ # Set max SATA speed to 6.0 Gb/s
+ register "sata_interface_speed_support" = "0x3"
+
+ register "gen1_dec" = "0x7c1601"
+ register "gen2_dec" = "0x0c15e1"
+ register "gen4_dec" = "0x0c06a1"
+
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ register "c2_latency" = "101" # c2 not supported
+ register "p_cnt_throttling_supported" = "1"
+
+ register "spi_uvscc" = "0x2005"
+ register "spi_lvscc" = "0x2005"
+
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on
+ subsystemid 0x17aa 0x21ce
+ end # Intel Gigabit Ethernet
+ device pci 1a.0 on
+ subsystemid 0x17aa 0x21e8
+ end # USB2 EHCI #2
+ device pci 1b.0 on
+ subsystemid 0x17aa 0x21e8
+ end # High Definition Audio
+ device pci 1c.0 on
+ subsystemid 0x17aa 0x21e8
+ end # PCIe Port #1
+ device pci 1c.1 on
+ subsystemid 0x17aa 0x21e8
+ end # PCIe Port #2 (wlan)
+ device pci 1c.2 on
+ subsystemid 0x17aa 0x21e8
+ end # PCIe Port #3
+ device pci 1c.3 on
+ subsystemid 0x17aa 0x21e8
+ end # PCIe Port #4
+ device pci 1c.4 on
+ subsystemid 0x17aa 0x21e8
+ chip drivers/ricoh/rce822 # Ricoh cardreader
+ register "sdwppol" = "1"
+ register "disable_mask" = "0x87"
+ device pci 00.0 on
+ subsystemid 0x17aa 0x21e8
+ end
+ end
+ end # PCIe Port #5 (SD)
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 on
+ subsystemid 0x17aa 0x21e8
+ end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on
+ subsystemid 0x17aa 0x21e8
+ end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on #LPC bridge
+ subsystemid 0x17aa 0x21e8
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa6"
+ register "config1" = "0x01"
+ register "config2" = "0xe0"
+ register "config3" = "0xc0"
+
+ register "has_keyboard_backlight" = "0"
+
+ register "beepmask0" = "0xfe"
+ register "beepmask1" = "0x96"
+ register "has_power_management_beeps" = "1"
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0x3c"
+ register "event6_enable" = "0x00"
+ register "event7_enable" = "0x81"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x3d"
+
+ # BDC detection is broken on this board:
+ # BDC shorts pin14 and pin1
+ # BDC's connector pin14 is left floating
+ # BDC's connector pin1 is routed to SB GPIO 54
+ register "has_bdc_detection" = "0"
+
+ register "has_wwan_detection" = "1"
+ register "wwan_gpio_num" = "70"
+ register "wwan_gpio_lvl" = "0"
+ end
+ end # LPC bridge
+ device pci 1f.2 on
+ subsystemid 0x17aa 0x21e8
+ end # SATA Controller 1
+ device pci 1f.3 on
+ subsystemid 0x17aa 0x21e8
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
+ end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on
+ subsystemid 0x17aa 0x21e8
+ end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/x220/variants/x1/gpio.c b/src/mainboard/lenovo/x220/variants/x1/gpio.c
new file mode 100644
index 0000000..e10bb1b
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x1/gpio.c
@@ -0,0 +1,220 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio1 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio42 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/variants/x220/devicetree.cb
similarity index 100%
rename from src/mainboard/lenovo/x220/devicetree.cb
rename to src/mainboard/lenovo/x220/variants/x220/devicetree.cb
diff --git a/src/mainboard/lenovo/x220/gpio.c b/src/mainboard/lenovo/x220/variants/x220/gpio.c
similarity index 100%
rename from src/mainboard/lenovo/x220/gpio.c
rename to src/mainboard/lenovo/x220/variants/x220/gpio.c
--
To view, visit https://review.coreboot.org/29434
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1
Gerrit-Change-Number: 29434
Gerrit-PatchSet: 1
Gerrit-Owner: Bill XIE <persmule at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181102/e5dd2f44/attachment-0001.html>
More information about the coreboot-gerrit
mailing list