<p>Bill XIE has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29434">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/lenovo/x220: Add x1 as a variant<br><br>ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a<br>clone of X220, with additional USB3 controller on pci-e (as i7 variant<br>of x220, and a powered ESATA port wired to ata4 (Linux' annotation).<br><br>Tested:<br>- CPU i5-2520M<br>- Slotted DIMM 8GiB<br>- Camera<br>- Mini pci-e on wlan slot<br>- Msata on wwan slot<br>- On board SDHCI connected to pci-e<br>- USB3 controller connected to pci-e<br>- NVRAM options for North and South bridges<br>- S3<br>- TPM1 on LPC<br>- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from<br> SeaBIOS, or Linux payload (Heads)<br><br>Not tested:<br>- Fingerprint reader on USB2<br>- Onboard USB2 interfaces (wlan slot, wwan slot)<br><br>Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1<br>Signed-off-by: Bill XIE <persmule@gmail.com><br>---<br>M src/mainboard/lenovo/x220/Kconfig<br>M src/mainboard/lenovo/x220/Kconfig.name<br>M src/mainboard/lenovo/x220/Makefile.inc<br>A src/mainboard/lenovo/x220/variants/x1/devicetree.cb<br>A src/mainboard/lenovo/x220/variants/x1/gpio.c<br>R src/mainboard/lenovo/x220/variants/x220/devicetree.cb<br>R src/mainboard/lenovo/x220/variants/x220/gpio.c<br>7 files changed, 450 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29434/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig</span><br><span>index a710c84..9a18e9b 100644</span><br><span>--- a/src/mainboard/lenovo/x220/Kconfig</span><br><span>+++ b/src/mainboard/lenovo/x220/Kconfig</span><br><span>@@ -1,4 +1,4 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span> def_bool y</span><br><span>@@ -30,9 +30,22 @@</span><br><span> string</span><br><span> default lenovo/x220</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VARIANT_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I</span><br><span style="color: hsl(120, 100%, 40%);">+ default "x1" if BOARD_LENOVO_X1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span style="color: hsl(0, 100%, 40%);">- default "ThinkPad X220"</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ThinkPad X220" if BOARD_LENOVO_X220</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ThinkPad X220i" if BOARD_LENOVO_X220I</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ThinkPad X1" if BOARD_LENOVO_X1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DEVICETREE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/x220/devicetree.cb" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I</span><br><span style="color: hsl(120, 100%, 40%);">+ default "variants/x1/devicetree.cb" if BOARD_LENOVO_X1</span><br><span> </span><br><span> config MAX_CPUS</span><br><span> int</span><br><span>@@ -49,6 +62,7 @@</span><br><span> config VGA_BIOS_FILE</span><br><span> string</span><br><span> default "pci8086,0116.rom" if BOARD_LENOVO_X220I</span><br><span style="color: hsl(120, 100%, 40%);">+ # FIXME: x1 with i3 cpu may also use "pci8086,0116.rom"</span><br><span> default "pci8086,0126.rom"</span><br><span> </span><br><span> config VGA_BIOS_ID</span><br><span>@@ -62,6 +76,11 @@</span><br><span> </span><br><span> config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span> hex</span><br><span style="color: hsl(0, 100%, 40%);">- default 0x21db</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x21db if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x21e8 if BOARD_LENOVO_X1</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I</span><br><span style="color: hsl(120, 100%, 40%);">+# Override the default variant behavior, since the data.vbt is the same</span><br><span style="color: hsl(120, 100%, 40%);">+config INTEL_GMA_VBT_FILE</span><br><span style="color: hsl(120, 100%, 40%);">+ default "src/mainboard/$(MAINBOARDDIR)/data.vbt"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1</span><br><span>diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name</span><br><span>index 0f9d3fc..988ac4f 100644</span><br><span>--- a/src/mainboard/lenovo/x220/Kconfig.name</span><br><span>+++ b/src/mainboard/lenovo/x220/Kconfig.name</span><br><span>@@ -3,3 +3,6 @@</span><br><span> </span><br><span> config BOARD_LENOVO_X220I</span><br><span> bool "ThinkPad X220i"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_LENOVO_X1</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "ThinkPad X1"</span><br><span>diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc</span><br><span>index 2dab950..ee968e2 100644</span><br><span>--- a/src/mainboard/lenovo/x220/Makefile.inc</span><br><span>+++ b/src/mainboard/lenovo/x220/Makefile.inc</span><br><span>@@ -14,6 +14,6 @@</span><br><span> ##</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += variants/$(VARIANT_DIR)/gpio.c</span><br><span> </span><br><span> ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads</span><br><span>diff --git a/src/mainboard/lenovo/x220/variants/x1/devicetree.cb b/src/mainboard/lenovo/x220/variants/x1/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..678c6c3</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/x220/variants/x1/devicetree.cb</span><br><span>@@ -0,0 +1,203 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/sandybridge</span><br><span style="color: hsl(120, 100%, 40%);">+ # IGD Displays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.ndid" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DisplayPort Hotplug with 6ms pulse</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_b_hotplug" = "0x04"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_c_hotplug" = "0x04"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_d_hotplug" = "0x04"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable Panel as LVDS and configure power delays</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_port_select" = "0" # LVDS</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_cycle_delay" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_down_delay" = "250" # T5+T6: 35ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_on_delay" = "2500" # T3: 250ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_off_delay" = "2500" # T4: 250ms</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.use_spread_spectrum_clock" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.link_frequency_270_mhz" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_cpu_backlight" = "0x1312"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_pch_backlight" = "0x13121312"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_rPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_206ax</span><br><span style="color: hsl(120, 100%, 40%);">+ # Magic APIC ID to locate this chip</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xACAC off end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pci_mmio_size" = "1024"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 off end # PCIe Bridge for discrete graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # vga controller</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPI routing</span><br><span style="color: hsl(120, 100%, 40%);">+ # 0 No effect (default)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)</span><br><span style="color: hsl(120, 100%, 40%);">+ # 2 SCI (if corresponding GPIO_EN bit is also set)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "alt_gp_smi_en" = "0x0000"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi1_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi13_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x1d"</span><br><span style="color: hsl(120, 100%, 40%);">+ # Set max SATA speed to 6.0 Gb/s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_interface_speed_support" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x7c1601"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x0c15e1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen4_dec" = "0x0c06a1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable zero-based linear PCIe root port functions</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_port_coalesce" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "101" # c2 not supported</span><br><span style="color: hsl(120, 100%, 40%);">+ register "p_cnt_throttling_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_uvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_lvscc" = "0x2005"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 off end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21ce</span><br><span style="color: hsl(120, 100%, 40%);">+ end # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # USB2 EHCI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # High Definition Audio</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #2 (wlan)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/ricoh/rce822 # Ricoh cardreader</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdwppol" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "disable_mask" = "0x87"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #5 (SD)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCIe Port #6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # PCIe Port #7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCIe Port #8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # USB2 EHCI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off end # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on #LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/pmh7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.1 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ register "backlight_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dock_event_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/h8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.2 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x64 = 0x1600</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x66 = 0x1604</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config0" = "0xa6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config1" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config2" = "0xe0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config3" = "0xc0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_keyboard_backlight" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask0" = "0xfe"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask1" = "0x96"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_power_management_beeps" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event2_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event3_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event4_enable" = "0xd0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event5_enable" = "0x3c"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event6_enable" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event7_enable" = "0x81"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event8_enable" = "0x7b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event9_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventc_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventd_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "evente_enable" = "0x3d"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # BDC detection is broken on this board:</span><br><span style="color: hsl(120, 100%, 40%);">+ # BDC shorts pin14 and pin1</span><br><span style="color: hsl(120, 100%, 40%);">+ # BDC's connector pin14 is left floating</span><br><span style="color: hsl(120, 100%, 40%);">+ # BDC's connector pin1 is routed to SB GPIO 54</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_bdc_detection" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "has_wwan_detection" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wwan_gpio_num" = "70"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "wwan_gpio_lvl" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # SATA Controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ # eeprom, 8 virtual devices, same chip</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/at24rf08c</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 54 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 55 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 56 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 57 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5c on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5d on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5e on end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5f on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off end # SATA Controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 on</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21e8</span><br><span style="color: hsl(120, 100%, 40%);">+ end # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/lenovo/x220/variants/x1/gpio.c b/src/mainboard/lenovo/x220/variants/x1/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..e10bb1b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/x220/variants/x1/gpio.c</span><br><span>@@ -0,0 +1,220 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio58 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio63 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio75 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/variants/x220/devicetree.cb</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/lenovo/x220/devicetree.cb</span><br><span>rename to src/mainboard/lenovo/x220/variants/x220/devicetree.cb</span><br><span>diff --git a/src/mainboard/lenovo/x220/gpio.c b/src/mainboard/lenovo/x220/variants/x220/gpio.c</span><br><span>similarity index 100%</span><br><span>rename from src/mainboard/lenovo/x220/gpio.c</span><br><span>rename to src/mainboard/lenovo/x220/variants/x220/gpio.c</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29434">change 29434</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 </div>
<div style="display:none"> Gerrit-Change-Number: 29434 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bill XIE <persmule@gmail.com> </div>