[coreboot-gerrit] Change in coreboot[master]: src/mainboard: Remove unneeded MSR header
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Thu May 31 14:58:51 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26733
Change subject: src/mainboard: Remove unneeded MSR header
......................................................................
src/mainboard: Remove unneeded MSR header
Change-Id: I3d4549ac9d5693c59d28d063255db376b4394e57
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/amd/lamar/mainboard.c
M src/mainboard/apple/macbookair4_2/early_southbridge.c
M src/mainboard/bap/ode_e21XX/mainboard.c
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/link/i915.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/stout/romstage.c
M src/mainboard/intel/cougar_canyon2/romstage.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/intel/harcuvar/acpi_tables.c
M src/mainboard/intel/stargo2/romstage.c
M src/mainboard/jetway/pa78vm5/mainboard.c
M src/mainboard/kontron/ktqm77/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t400/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x200/romstage.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x230/romstage.c
M src/mainboard/roda/rk9/romstage.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/sapphire/pureplatinumh61/romstage.c
M src/mainboard/scaleway/tagada/acpi_tables.c
29 files changed, 0 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/26733/1
diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c
index 94e680b..706ea9f 100644
--- a/src/mainboard/amd/lamar/mainboard.c
+++ b/src/mainboard/amd/lamar/mainboard.c
@@ -19,7 +19,6 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <arch/acpi.h>
-#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/pi/00630F01/pci_devs.h>
#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c
index 25ddb98..6d2cbd1 100644
--- a/src/mainboard/apple/macbookair4_2/early_southbridge.c
+++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c
@@ -28,7 +28,6 @@
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <cbfs.h>
void pch_enable_lpc(void)
diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c
index 1e8d723..e537f25 100644
--- a/src/mainboard/bap/ode_e21XX/mainboard.c
+++ b/src/mainboard/bap/ode_e21XX/mainboard.c
@@ -19,7 +19,6 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <arch/acpi.h>
-#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
/**********************************************
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index 92bef28..858d08e 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -32,7 +32,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
{
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index 283ad46..ae22309 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -32,7 +32,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
{
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index ebcba84..88ae638 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -33,7 +33,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <halt.h>
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 9ab3149..2e228a9 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -38,7 +38,6 @@
#include <cpu/x86/tsc.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
#include <edid.h>
#include "i915io.h"
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index a1bbe34..a6630cf 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -34,7 +34,6 @@
#include <southbridge/intel/common/gpio.h>
#include "ec/google/chromeec/ec.h"
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <halt.h>
#include <security/tpm/tis.h>
#include <cbfs.h>
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 12c1114..dfcd6e3 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -33,7 +33,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <halt.h>
#include <cbfs.h>
#include <security/tpm/tis.h>
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 4f7f869..70115e4 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -33,7 +33,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <halt.h>
#include <bootmode.h>
#include <security/tpm/tis.h>
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 96c22ea..c6a07d5 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -38,7 +38,6 @@
#include <southbridge/intel/fsp_bd82x6x/gpio.h>
#include <southbridge/intel/fsp_bd82x6x/me.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include "gpio.h"
#define SIO_PORT 0x164e
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 24c4b56..c2eab1f 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -34,7 +34,6 @@
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <halt.h>
#include <security/tpm/tis.h>
diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c
index acbdb30..d6a5dbd 100644
--- a/src/mainboard/intel/harcuvar/acpi_tables.c
+++ b/src/mainboard/intel/harcuvar/acpi_tables.c
@@ -27,7 +27,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
diff --git a/src/mainboard/intel/stargo2/romstage.c b/src/mainboard/intel/stargo2/romstage.c
index ff90e2e..9af714e 100644
--- a/src/mainboard/intel/stargo2/romstage.c
+++ b/src/mainboard/intel/stargo2/romstage.c
@@ -24,7 +24,6 @@
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-#include <cpu/x86/msr.h>
#include <pc80/mc146818rtc.h>
#include <cbmem.h>
#include <console/console.h>
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index ab305e3..1725338 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index bff4991..eb1e806 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -33,7 +33,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <halt.h>
void pch_enable_lpc(void)
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index 83664f4..426bd42 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -31,7 +31,6 @@
#include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include "ec.h"
#define SPD_LEN 256
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index fd3544e..b1d5db6 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -21,7 +21,6 @@
#include <arch/io.h>
#include <arch/acpi.h>
#include <cpu/x86/lapic.h>
-#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <cpu/intel/romstage.h>
#include <cbmem.h>
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 638e7ca..8f17076 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -34,7 +34,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <cbfs.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <device/device.h>
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
index 2c148d4..420c4d6 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
@@ -25,7 +25,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/nvs.h>
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index 029d867..3c8b8be 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -34,7 +34,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <cbfs.h>
void pch_enable_lpc(void)
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 71de550..30f1119 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -21,7 +21,6 @@
#include <arch/io.h>
#include <arch/acpi.h>
#include <cpu/x86/lapic.h>
-#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <cpu/intel/romstage.h>
#include <cbmem.h>
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index e38dfe7..1a091d6 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -33,7 +33,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
void pch_enable_lpc(void)
{
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 7801d57..4bea13c 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -34,7 +34,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <cbfs.h>
void pch_enable_lpc(void)
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 65ff0f8..708eb5d 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -20,7 +20,6 @@
#include <string.h>
#include <arch/io.h>
#include <cpu/x86/lapic.h>
-#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <cpu/intel/romstage.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index ce17068..c989662 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -36,7 +36,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <halt.h>
#include "option_table.h"
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 0da658c..3d6707c 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -36,7 +36,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <halt.h>
#include <security/tpm/tis.h>
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
index 420a956..ddcd46b 100644
--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -31,7 +31,6 @@
#include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
#include <delay.h>
void pch_enable_lpc(void)
diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c
index acbdb30..d6a5dbd 100644
--- a/src/mainboard/scaleway/tagada/acpi_tables.c
+++ b/src/mainboard/scaleway/tagada/acpi_tables.c
@@ -27,7 +27,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3d4549ac9d5693c59d28d063255db376b4394e57
Gerrit-Change-Number: 26733
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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