[coreboot-gerrit] Change in coreboot[master]: cpu/intel/haswell: Use postcar stage to tear down CAR
Arthur Heymans (Code Review)
gerrit at coreboot.org
Thu May 31 01:10:15 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26719
Change subject: cpu/intel/haswell: Use postcar stage to tear down CAR
......................................................................
cpu/intel/haswell: Use postcar stage to tear down CAR
Also use common postcar function to set up the postcar frame instead
'manually' pushing stuff to the stack.
Change-Id: I643102576f4b7afe42022af7ea14c12683b715ce
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/haswell/Kconfig
M src/cpu/intel/haswell/Makefile.inc
M src/cpu/intel/haswell/cache_as_ram.inc
M src/cpu/intel/haswell/romstage.c
M src/northbridge/intel/haswell/Makefile.inc
5 files changed, 25 insertions(+), 182 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/26719/1
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
index 9076b88..262a72f 100644
--- a/src/cpu/intel/haswell/Kconfig
+++ b/src/cpu/intel/haswell/Kconfig
@@ -26,6 +26,8 @@
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select PARALLEL_MP
select CPU_INTEL_COMMON
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index bb0f376..c050300 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -9,12 +9,14 @@
ramstage-y += monotonic_timer.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-y += monotonic_timer.c
cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc
+postcar-y += ../model_206ax/teardown_car.S
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 2094940..c14f801 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -188,108 +188,7 @@
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
- /* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down. It also contains the information
- * for setting up MTRRs. */
- movl %eax, %esp
-
- post_code(0x30)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x31)
-
- /* Disable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- andl $(~MTRR_DEF_TYPE_EN), %eax
- wrmsr
-
- post_code(0x32)
-
- /* Disable the no eviction run state */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- andl $~2, %eax
- wrmsr
-
- invd
-
- /* Disable the no eviction mode */
- rdmsr
- andl $~1, %eax
- wrmsr
-
- post_code(0x33)
-
- /* Enable cache. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x36)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x38)
-
- /* Get number of MTRRs. */
- popl %ebx
- movl $MTRR_PHYS_BASE(0), %ecx
-1:
- testl %ebx, %ebx
- jz 1f
-
- /* Low 32 bits of MTRR base. */
- popl %eax
- /* Upper 32 bits of MTRR base. */
- popl %edx
- /* Write MTRR base. */
- wrmsr
- inc %ecx
- /* Low 32 bits of MTRR mask. */
- popl %eax
- /* Upper 32 bits of MTRR mask. */
- popl %edx
- /* Write MTRR mask. */
- wrmsr
- inc %ecx
-
- dec %ebx
- jmp 1b
-1:
- post_code(0x39)
-
- /* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x3a)
-
- /* Enable MTRR. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- orl $MTRR_DEF_TYPE_EN, %eax
- wrmsr
-
- post_code(0x3b)
-
- /* Invalidate the cache again. */
- invd
-
- post_code(0x3c)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
- call romstage_after_car
+ /* We don't return here */
.Lhlt:
post_code(POST_DEAD_CODE)
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 6d9fbc4..7a2a558 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -50,100 +50,37 @@
halt();
}
-/* The cache-as-ram assembly file calls romstage_main() after setting up
- * cache-as-ram. romstage_main() will then call the mainboards's
- * mainboard_romstage_entry() function. That function then calls
- * romstage_common() below. The reason for the back and forth is to provide
- * common entry point from cache-as-ram while still allowing for code sharing.
- * Because we can't use global variables the stack is used for allocations --
- * thus the need to call back and forth. */
-
-
-static inline u32 *stack_push(u32 *stack, u32 value)
-{
- stack = &stack[-1];
- *stack = value;
- return stack;
-}
-
/* setup_romstage_stack_after_car() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
-static void *setup_romstage_stack_after_car(void)
+static void setup_romstage_stack_after_car(void)
{
- int num_mtrrs;
- u32 *slot;
- u32 mtrr_mask_upper;
+ struct postcar_frame pcf;
u32 top_of_ram;
- /* Top of stack needs to be aligned to a 4-byte boundary. */
- slot = (void *)romstage_ram_stack_top();
- num_mtrrs = 0;
-
- /* The upper bits of the MTRR mask need to set according to the number
- * of physical address bits. */
- mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1;
-
- /* The order for each MTRR is value then base with upper 32-bits of
- * each value coming before the lower 32-bits. The reasoning for
- * this ordering is to create a stack layout like the following:
- * +0: Number of MTRRs
- * +4: MTRR base 0 31:0
- * +8: MTRR base 0 63:32
- * +12: MTRR mask 0 31:0
- * +16: MTRR mask 0 63:32
- * +20: MTRR base 1 31:0
- * +24: MTRR base 1 63:32
- * +28: MTRR mask 1 31:0
- * +32: MTRR mask 1 63:32
- */
+ if (postcar_frame_init(&pcf, 1*KiB))
+ die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
- num_mtrrs++;
+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
- num_mtrrs++;
+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
- top_of_ram = (uint32_t)cbmem_top();
- /* Cache 8MiB below the top of RAM. On haswell systems the top of
- * RAM under 4GiB is the start of the TSEG region. It is required to
- * be 8MiB aligned. Set this area as cacheable so it can be used later
- * for ramstage before setting up the entire RAM as cacheable. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
- num_mtrrs++;
+ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+ * above top of the ram. This satisfies MTRR alignment requirement
+ * with different TSEG size configurations.
+ */
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
+ MTRR_TYPE_WRBACK);
- /* Cache 8MiB at the top of RAM. Top of RAM on haswell systems
- * is where the TSEG region resides. However, it is not restricted
- * to SMM mode until SMM has been relocated. By setting the region
- * to cacheable it provides faster access when relocating the SMM
- * handler as well as using the TSEG region for other purposes. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs. */
- slot = stack_push(slot, num_mtrrs);
-
- return slot;
+ run_postcar_phase(&pcf);
}
asmlinkage void *romstage_main(unsigned long bist)
{
int i;
- void *romstage_stack_after_car;
const int num_guards = 4;
const u32 stack_guard = 0xdeadbeef;
u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
@@ -164,9 +101,10 @@
}
/* Get the stack to use after cache-as-ram is torn down. */
- romstage_stack_after_car = setup_romstage_stack_after_car();
+ setup_romstage_stack_after_car();
- return romstage_stack_after_car;
+ /* We don't return here */
+ return NULL;
}
void romstage_common(const struct romstage_params *params)
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index c6d6b2e..055c2a8 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -36,4 +36,6 @@
mrc.bin-position := 0xfffa0000
mrc.bin-type := mrc
+postcar-y += ram_calc.c
+
endif
--
To view, visit https://review.coreboot.org/26719
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I643102576f4b7afe42022af7ea14c12683b715ce
Gerrit-Change-Number: 26719
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180530/7c23744d/attachment-0001.html>
More information about the coreboot-gerrit
mailing list