<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26719">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/haswell: Use postcar stage to tear down CAR<br><br>Also use common postcar function to set up the postcar frame instead<br>'manually' pushing stuff to the stack.<br><br>Change-Id: I643102576f4b7afe42022af7ea14c12683b715ce<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/haswell/Kconfig<br>M src/cpu/intel/haswell/Makefile.inc<br>M src/cpu/intel/haswell/cache_as_ram.inc<br>M src/cpu/intel/haswell/romstage.c<br>M src/northbridge/intel/haswell/Makefile.inc<br>5 files changed, 25 insertions(+), 182 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/26719/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig</span><br><span>index 9076b88..262a72f 100644</span><br><span>--- a/src/cpu/intel/haswell/Kconfig</span><br><span>+++ b/src/cpu/intel/haswell/Kconfig</span><br><span>@@ -26,6 +26,8 @@</span><br><span> select CPU_INTEL_FIRMWARE_INTERFACE_TABLE</span><br><span> select PARALLEL_MP</span><br><span> select CPU_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_STAGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select POSTCAR_CONSOLE</span><br><span> </span><br><span> config BOOTBLOCK_CPU_INIT</span><br><span> string</span><br><span>diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc</span><br><span>index bb0f376..c050300 100644</span><br><span>--- a/src/cpu/intel/haswell/Makefile.inc</span><br><span>+++ b/src/cpu/intel/haswell/Makefile.inc</span><br><span>@@ -9,12 +9,14 @@</span><br><span> ramstage-y += monotonic_timer.c</span><br><span> </span><br><span> romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c</span><br><span> smm-y += monotonic_timer.c</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/intel/haswell/cache_as_ram.inc</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ../model_206ax/teardown_car.S</span><br><span> </span><br><span> subdirs-y += ../../x86/tsc</span><br><span> subdirs-y += ../../x86/mtrr</span><br><span>diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc</span><br><span>index 2094940..c14f801 100644</span><br><span>--- a/src/cpu/intel/haswell/cache_as_ram.inc</span><br><span>+++ b/src/cpu/intel/haswell/cache_as_ram.inc</span><br><span>@@ -188,108 +188,7 @@</span><br><span> post_code(0x29)</span><br><span> /* Call romstage.c main function. */</span><br><span> call romstage_main</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save return value from romstage_main. It contains the stack to use</span><br><span style="color: hsl(0, 100%, 40%);">- * after cache-as-ram is torn down. It also contains the information</span><br><span style="color: hsl(0, 100%, 40%);">- * for setting up MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %esp</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x30)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x31)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $(~MTRR_DEF_TYPE_EN), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x32)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction run state */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $NoEvictMod_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~2, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable the no eviction mode */</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~1, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x33)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x36)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable cache. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- orl $CR0_CacheDisable, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x38)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Get number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_PHYS_BASE(0), %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- testl %ebx, %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jz 1f</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR base. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Low 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %eax</span><br><span style="color: hsl(0, 100%, 40%);">- /* Upper 32 bits of MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- popl %edx</span><br><span style="color: hsl(0, 100%, 40%);">- /* Write MTRR mask. */</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">- inc %ecx</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dec %ebx</span><br><span style="color: hsl(0, 100%, 40%);">- jmp 1b</span><br><span style="color: hsl(0, 100%, 40%);">-1:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x39)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* And enable cache again after setting MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl %cr0, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax</span><br><span style="color: hsl(0, 100%, 40%);">- movl %eax, %cr0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3a)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable MTRR. */</span><br><span style="color: hsl(0, 100%, 40%);">- movl $MTRR_DEF_TYPE_MSR, %ecx</span><br><span style="color: hsl(0, 100%, 40%);">- rdmsr</span><br><span style="color: hsl(0, 100%, 40%);">- orl $MTRR_DEF_TYPE_EN, %eax</span><br><span style="color: hsl(0, 100%, 40%);">- wrmsr</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3b)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Invalidate the cache again. */</span><br><span style="color: hsl(0, 100%, 40%);">- invd</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(0x3c)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-__main:</span><br><span style="color: hsl(0, 100%, 40%);">- post_code(POST_PREPARE_RAMSTAGE)</span><br><span style="color: hsl(0, 100%, 40%);">- cld /* Clear direction flag. */</span><br><span style="color: hsl(0, 100%, 40%);">- call romstage_after_car</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span> </span><br><span> .Lhlt:</span><br><span> post_code(POST_DEAD_CODE)</span><br><span>diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c</span><br><span>index 6d9fbc4..7a2a558 100644</span><br><span>--- a/src/cpu/intel/haswell/romstage.c</span><br><span>+++ b/src/cpu/intel/haswell/romstage.c</span><br><span>@@ -50,100 +50,37 @@</span><br><span> halt();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* The cache-as-ram assembly file calls romstage_main() after setting up</span><br><span style="color: hsl(0, 100%, 40%);">- * cache-as-ram. romstage_main() will then call the mainboards's</span><br><span style="color: hsl(0, 100%, 40%);">- * mainboard_romstage_entry() function. That function then calls</span><br><span style="color: hsl(0, 100%, 40%);">- * romstage_common() below. The reason for the back and forth is to provide</span><br><span style="color: hsl(0, 100%, 40%);">- * common entry point from cache-as-ram while still allowing for code sharing.</span><br><span style="color: hsl(0, 100%, 40%);">- * Because we can't use global variables the stack is used for allocations --</span><br><span style="color: hsl(0, 100%, 40%);">- * thus the need to call back and forth. */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static inline u32 *stack_push(u32 *stack, u32 value)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- stack = &stack[-1];</span><br><span style="color: hsl(0, 100%, 40%);">- *stack = value;</span><br><span style="color: hsl(0, 100%, 40%);">- return stack;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* setup_romstage_stack_after_car() determines the stack to use after</span><br><span> * cache-as-ram is torn down as well as the MTRR settings to use. */</span><br><span style="color: hsl(0, 100%, 40%);">-static void *setup_romstage_stack_after_car(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static void setup_romstage_stack_after_car(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- int num_mtrrs;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 *slot;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 mtrr_mask_upper;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct postcar_frame pcf;</span><br><span> u32 top_of_ram;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Top of stack needs to be aligned to a 4-byte boundary. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = (void *)romstage_ram_stack_top();</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs = 0;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The upper bits of the MTRR mask need to set according to the number</span><br><span style="color: hsl(0, 100%, 40%);">- * of physical address bits. */</span><br><span style="color: hsl(0, 100%, 40%);">- mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* The order for each MTRR is value then base with upper 32-bits of</span><br><span style="color: hsl(0, 100%, 40%);">- * each value coming before the lower 32-bits. The reasoning for</span><br><span style="color: hsl(0, 100%, 40%);">- * this ordering is to create a stack layout like the following:</span><br><span style="color: hsl(0, 100%, 40%);">- * +0: Number of MTRRs</span><br><span style="color: hsl(0, 100%, 40%);">- * +4: MTRR base 0 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +8: MTRR base 0 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +12: MTRR mask 0 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +16: MTRR mask 0 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +20: MTRR base 1 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +24: MTRR base 1 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- * +28: MTRR mask 1 31:0</span><br><span style="color: hsl(0, 100%, 40%);">- * +32: MTRR mask 1 63:32</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (postcar_frame_init(&pcf, 1*KiB))</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Unable to initialize postcar frame.\n");</span><br><span> </span><br><span> /* Cache the ROM as WP just below 4GiB. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0); /* upper base */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs++;</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRPROT);</span><br><span> </span><br><span> /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0); /* upper base */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs++;</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- top_of_ram = (uint32_t)cbmem_top();</span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache 8MiB below the top of RAM. On haswell systems the top of</span><br><span style="color: hsl(0, 100%, 40%);">- * RAM under 4GiB is the start of the TSEG region. It is required to</span><br><span style="color: hsl(0, 100%, 40%);">- * be 8MiB aligned. Set this area as cacheable so it can be used later</span><br><span style="color: hsl(0, 100%, 40%);">- * for ramstage before setting up the entire RAM as cacheable. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0); /* upper base */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs++;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB</span><br><span style="color: hsl(120, 100%, 40%);">+ * above top of the ram. This satisfies MTRR alignment requirement</span><br><span style="color: hsl(120, 100%, 40%);">+ * with different TSEG size configurations.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);</span><br><span style="color: hsl(120, 100%, 40%);">+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,</span><br><span style="color: hsl(120, 100%, 40%);">+ MTRR_TYPE_WRBACK);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Cache 8MiB at the top of RAM. Top of RAM on haswell systems</span><br><span style="color: hsl(0, 100%, 40%);">- * is where the TSEG region resides. However, it is not restricted</span><br><span style="color: hsl(0, 100%, 40%);">- * to SMM mode until SMM has been relocated. By setting the region</span><br><span style="color: hsl(0, 100%, 40%);">- * to cacheable it provides faster access when relocating the SMM</span><br><span style="color: hsl(0, 100%, 40%);">- * handler as well as using the TSEG region for other purposes. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, 0); /* upper base */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);</span><br><span style="color: hsl(0, 100%, 40%);">- num_mtrrs++;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Save the number of MTRRs to setup. Return the stack location</span><br><span style="color: hsl(0, 100%, 40%);">- * pointing to the number of MTRRs. */</span><br><span style="color: hsl(0, 100%, 40%);">- slot = stack_push(slot, num_mtrrs);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return slot;</span><br><span style="color: hsl(120, 100%, 40%);">+ run_postcar_phase(&pcf);</span><br><span> }</span><br><span> </span><br><span> asmlinkage void *romstage_main(unsigned long bist)</span><br><span> {</span><br><span> int i;</span><br><span style="color: hsl(0, 100%, 40%);">- void *romstage_stack_after_car;</span><br><span> const int num_guards = 4;</span><br><span> const u32 stack_guard = 0xdeadbeef;</span><br><span> u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +</span><br><span>@@ -164,9 +101,10 @@</span><br><span> }</span><br><span> </span><br><span> /* Get the stack to use after cache-as-ram is torn down. */</span><br><span style="color: hsl(0, 100%, 40%);">- romstage_stack_after_car = setup_romstage_stack_after_car();</span><br><span style="color: hsl(120, 100%, 40%);">+ setup_romstage_stack_after_car();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- return romstage_stack_after_car;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* We don't return here */</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span> }</span><br><span> </span><br><span> void romstage_common(const struct romstage_params *params)</span><br><span>diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>index c6d6b2e..055c2a8 100644</span><br><span>--- a/src/northbridge/intel/haswell/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>@@ -36,4 +36,6 @@</span><br><span> mrc.bin-position := 0xfffa0000</span><br><span> mrc.bin-type := mrc</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+postcar-y += ram_calc.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26719">change 26719</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I643102576f4b7afe42022af7ea14c12683b715ce </div>
<div style="display:none"> Gerrit-Change-Number: 26719 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>